Semiconductor & Computer Engineering
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Difference between revisions of "amd/am486/am486dx4-100v16b"
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{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1 cache= | + | |l1 cache=16 KiB |
| − | |l1 break= | + | |l1 break=1x16 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
| − | |l1 extra=(unified, write- | + | |l1 extra=(unified, write-back policy) |
}} | }} | ||
Revision as of 21:45, 20 September 2016
Template:mpu Am486DX2-66V16B was an Enhanced Am486 microprocessor introduced by AMD in 1997. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model had larger L1 cache of 16 KB with Write-Back policy. This model has twice as much cache as the Am486DX4-100V8T model (previously Am486DX4-100). This "Enhanced" Am486 includes some other features such as SMM.
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative (unified, write-back policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
Packaging
| Part Number | Package | Type | Temperature Range |
|---|---|---|---|
| Am486DX4-100V16BHC | SQFP-208 | Commercial | 0 °C to 85 °C |
| Am486DX4-100V16BGC | CPGA-168 | Commercial | 0 °C to 85 °C |
| Am486DX4-100V16BHI | SQFP-208 | Industrial | -40 °C to 100 °C |
| Am486DX4-100V16BGI | CPGA-168 | Industrial | -40 °C to 100 °C |
See also
Facts about "Am486DX4-100V16B - AMD"
| has feature | System Management Mode + |
| l1$ description | 4-way set associative + |
| l1$ size | 16 KiB (16,384 B, 0.0156 MiB) + |