From WikiChip
Difference between revisions of "amd/am186/sb80c186-12"
(→Cache) |
|||
Line 79: | Line 79: | ||
{{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}} | {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}} | ||
{{cache info | {{cache info | ||
− | |l1 cache=0 | + | |l1 cache=0 KiB |
− | |l1 break=1x0 | + | |l1 break=1x0 KiB |
|l1 desc= | |l1 desc= | ||
|l1 extra= | |l1 extra= | ||
− | |l2 cache=0 | + | |l2 cache=0 KiB |
− | |l2 break=1x0 | + | |l2 break=1x0 KiB |
}} | }} | ||
Revision as of 21:21, 20 September 2016
Template:mpu SB80C186-12 is an 80186-based microprocessor manufactured by AMD in TQFP-80 packages. This model is a redesigned CMOS version that operated at 12.5 MHz and introduced a number of enhancements in addition to being lower-power CMOS, including a DRAM Refresh Control Unit and various power saving modes.
Contents
Cache
- Main article: 80186 § Cache
Cache Info [Edit Values] | ||
L1$ | 0 KiB 0 B 0 MiB |
1x0 KiB |
L2$ | 0 KiB 0 MiB 0 B 0 GiB |
1x0 KiB |
Graphics
This chip had no integrated graphics processing unit.
Features
- 10 new instructions
- Two DMA channels
- Three programmable interrupt timers
- Local Bus Controller
- Object code-compatible with all 86/88 software
- Power saving mode
- DRAM Refresh Control Unit
Documents
- AMD 80C186 (June 1994), Publication #17907 Rev B