From WikiChip
Difference between revisions of "intel/xeon e7/e7-4860"
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− | |l3 cache=24 | + | |l3 cache=24 MiB |
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|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
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Revision as of 02:08, 19 September 2016
Template:mpu Xeon E7-4860 is a 64-bit deca-core x86 data center microprocessor that supports up to 4 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2.26 GHz with turob frequency of 2.66 GHz for 2 active cores. This chip has a TDP of 130 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.
Contents
Cache
- Main article: Westmere § Cache
Cache Info [Edit Values] | ||
L1I$ | 320 KB "KB" is not declared as a valid unit of measurement for this property. |
10x32 KB 4-way set associative (per core) |
L1D$ | 320 KB "KB" is not declared as a valid unit of measurement for this property. |
10x32 KB 8-way set associative (per core) |
L2$ | 2.56 MB "MB" is not declared as a valid unit of measurement for this property. |
10x256 KB 8-way set associative (per core) |
L3$ | 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB |
16-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR3-800, DDR3-978, DDR3-1066 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max memory | 2048 GB |
Features
Facts about "Xeon E7-4860 - Intel"
l1d$ description | 8-way set associative + |
l1i$ description | 4-way set associative + |
l2$ description | 8-way set associative + |
l3$ description | 16-way set associative + |
l3$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |