Semiconductor & Computer Engineering
| Line 77: | Line 77: | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
}} | }} | ||
| − | '''PEZY-SC''' ('''PEZY Super Computer''') is second generation [[many-core microprocessor]] developed by [[PEZY]] in 2014. PEZY-SC contains 2 {{armh|ARM926}} cores ({{arm|ARMv5TEJ}}) along with 1024 simpler RISC cores. Operating at 733 MHz, the processor is said to have peach performance of 3.0 TFLOPS (single-precision) and 1.5 TFLOPS (double-precision). PEZY-SC was designed using 580 million gates and manufactured on TSMC's [[28 nm process]]. | + | '''PEZY-SC''' ('''PEZY Super Computer''') is second generation [[many-core microprocessor]] developed by [[PEZY]] in 2014. PEZY-SC contains 2 {{armh|ARM926}} cores ({{arm|ARMv5TEJ}}) along with 1024 simpler RISC cores. Operating at 733 MHz, the processor is said to have peach performance of 3.0 TFLOPS (single-precision) and 1.5 TFLOPS (double-precision). PEZY-SC was designed using 580 million gates and manufactured on TSMC's [[28 nm process]]. The PEZY-SC is used in a number of [[TOP500]] & [[Green500]] supercomputers as the world's most efficient supercomputers. |
| + | |||
| + | == Overview == | ||
| + | {{see also|pezy/pezy-1|l1=PEZY-1}} | ||
| + | The PEZY-SC (SC for "Super Computer") is [[PEZY]]'s second generation microprocessors which builds upon the {{pezy|PEZY-1}}. The chip contains exactly twice as many cores and incorporates a large amount of cache including 8 MB of L3$. | ||
In June of 2015, PEZY-SC-based [[supercomputer]]s took all top 3 spots on the [[Green500]] listing as the 3 most efficient supercomputers. PEZY-SC powers [[Shoubu]] (1,181,952 cores, ? kW, 605.624 TFlop/s [[Linpack]] Rmax), and [[Suiren Blue]] (262,656 cores, 40.86 kW, 247.752 TFlop/s Linpack Rmax), and [[Suiren]] (328,480 cores, 48.90 kW, 271.782 TFlop/s Linpack Rmax) supercomputers (ranked 1, 2, and 3 respectively). | In June of 2015, PEZY-SC-based [[supercomputer]]s took all top 3 spots on the [[Green500]] listing as the 3 most efficient supercomputers. PEZY-SC powers [[Shoubu]] (1,181,952 cores, ? kW, 605.624 TFlop/s [[Linpack]] Rmax), and [[Suiren Blue]] (262,656 cores, 40.86 kW, 247.752 TFlop/s Linpack Rmax), and [[Suiren]] (328,480 cores, 48.90 kW, 271.782 TFlop/s Linpack Rmax) supercomputers (ranked 1, 2, and 3 respectively). | ||
| + | |||
| + | == Cache == | ||
| + | PEZY-SC's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 32KB (2x) and 64KB L2$ (shared). | ||
| + | {{cache info | ||
| + | |l1 cache=1 MB | ||
| + | |l1 break= | ||
| + | |l1 desc= | ||
| + | |l1 extra= | ||
| + | |l2 cache=4 MB | ||
| + | |l2 break= | ||
| + | |l2 desc= | ||
| + | |l2 extra= | ||
| + | |l3 cache=8 MB | ||
| + | |l3 desc= | ||
| + | }} | ||
| + | |||
| + | == Memory controller == | ||
| + | {{integrated memory controller | ||
| + | | type = DDR4-2400 | ||
| + | | controllers = 1 | ||
| + | | channels = 8 | ||
| + | | ecc support = <!-- ?? --> | ||
| + | | bandwidth schan = 19,200 MB/s | ||
| + | | bandwidth dchan = 38,400 MB/s | ||
| + | | bandwidth qchan = 76,800 MB/s | ||
| + | | bandwidth ochan = 153,600 MB/s | ||
| + | | max memory = | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | {{mpu expansions | ||
| + | | pcie revision = 3.0 | ||
| + | | pcie lanes = 8 | ||
| + | | pcie config = | ||
| + | | pcie config 1 = | ||
| + | | pcie config 2 = | ||
| + | | usb revision = | ||
| + | | usb revision 2 = | ||
| + | | usb ports = | ||
| + | | sata revision = | ||
| + | | sata ports = | ||
| + | | integrated lan = | ||
| + | | uart = | ||
| + | | gp io = | ||
| + | }} | ||
== External Links == | == External Links == | ||
Revision as of 15:41, 6 September 2016
Template:mpu PEZY-SC (PEZY Super Computer) is second generation many-core microprocessor developed by PEZY in 2014. PEZY-SC contains 2 ARM926 cores (ARMv5TEJ) along with 1024 simpler RISC cores. Operating at 733 MHz, the processor is said to have peach performance of 3.0 TFLOPS (single-precision) and 1.5 TFLOPS (double-precision). PEZY-SC was designed using 580 million gates and manufactured on TSMC's 28 nm process. The PEZY-SC is used in a number of TOP500 & Green500 supercomputers as the world's most efficient supercomputers.
Overview
- See also: PEZY-1
The PEZY-SC (SC for "Super Computer") is PEZY's second generation microprocessors which builds upon the PEZY-1. The chip contains exactly twice as many cores and incorporates a large amount of cache including 8 MB of L3$.
In June of 2015, PEZY-SC-based supercomputers took all top 3 spots on the Green500 listing as the 3 most efficient supercomputers. PEZY-SC powers Shoubu (1,181,952 cores, ? kW, 605.624 TFlop/s Linpack Rmax), and Suiren Blue (262,656 cores, 40.86 kW, 247.752 TFlop/s Linpack Rmax), and Suiren (328,480 cores, 48.90 kW, 271.782 TFlop/s Linpack Rmax) supercomputers (ranked 1, 2, and 3 respectively).
Cache
PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32KB (2x) and 64KB L2$ (shared).
| Cache Info [Edit Values] | ||
| L1$ | 1 MB "MB" is not declared as a valid unit of measurement for this property. |
|
| L2$ | 4 MB "MB" is not declared as a valid unit of measurement for this property. |
|
| L3$ | 8 MB "MB" is not declared as a valid unit of measurement for this property. |
|
Memory controller
| Integrated Memory Controller | |
| Type | DDR4-2400 |
| Controllers | 1 |
| Channels | 8 |
| Bandwidth (single) | 19,200 MB/s |
| Bandwidth (dual) | 38,400 MB/s |
| Bandwidth (quad) | 76,800 MB/s |
| Bandwidth (octa) | 153,600 MB/s |