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Difference between revisions of "intel/celeron/j3455"
< intel‎ | celeron

(+gpu)
(expansion + features)
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* Video decode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, MPEG2, VC-1, WMV9, JPEG/MJPEG.
 
* Video decode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, MPEG2, VC-1, WMV9, JPEG/MJPEG.
 
* Video encode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, JPEG/MJPEG.
 
* Video encode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, JPEG/MJPEG.
 +
 +
== Expansions ==
 +
{{mpu expansions
 +
| pcie revision      = 2.0
 +
| pcie lanes        = 6
 +
| pcie config        = 4x1
 +
| pcie config 1      = 1x4 + 1x2
 +
| pcie config 2      = 2x1 + 1x2 + 1x2
 +
| usb revision      = 2.0
 +
| usb revision 2    = 3.0
 +
| usb ports          = 8
 +
| sata revision      = 3.0
 +
| sata ports        = 3
 +
| integrated lan    =
 +
| uart              = Yes
 +
| gp io              = Yes
 +
}}
 +
 +
* 2x USB 2.0 ports
 +
* 6x USB 3.0 ports
 +
** 1x USB Dual Role
 +
** 1x Dedicated Port
 +
** 3x multiplexed with PCIe 2.0
 +
** 1x multiplexed with SATA 3.0
 +
 +
== Features ==
 +
{{mpu features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        =
 +
| vpro        =
 +
| ht          =
 +
| tbt1        =
 +
| tbt2        =
 +
| bpt        = Yes
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        =
 +
| avx2        =
 +
| bmi        =
 +
| bmi1        =
 +
| bmi2        =
 +
| f16c        =
 +
| fma3        =
 +
| mpx        =
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    =
 +
| intel at    =
 +
}}

Revision as of 23:42, 5 September 2016

Template:mpu Celeron J3455 is a quad-core 64-bit x86 desktop microprocessor introduced by Intel in 2016. The processor is based on Goldmont microarchitecture and is manufactured on a 14 nm process. The chip operates at 1.5 GHz with burst frequency of 2.3 GHz and has a TDP of 10 W. This MPU incorporates Intel's HD Graphics 500 GPU operating at 250 MHz with a burst frequency of 750 MHz.

Cache

Main article: Goldmont's Cache
Cache Info [Edit Values]
L1I$ 128 KB
"KB" is not declared as a valid unit of measurement for this property.
 		4x32 KB 8-way set associative (per core)
L1D$ 96 KB
"KB" is not declared as a valid unit of measurement for this property.
 		4x24 KB 6-way set associative (per core)
L2$ 2 MB
"MB" is not declared as a valid unit of measurement for this property.
 		2x1 MB 16-way set associative (per 2 cores)
L3$ 0 KB
"KB" is not declared as a valid unit of measurement for this property.
 		No L3$

Memory controller

Integrated Memory Controller
Type LPDDR3-1333, LPDDR3-1600, LPDDR3-2400, DDR3L-1333, DDR3L-1600, DDR3L-1867, LPDDR4-1600, LPDDR4-2133, LPDDR4-2400
Controllers 1
Channels 2
ECC Support No
Bandwidth (single) 19,200 MB/s
Bandwidth (dual) 38,400 MB/s
Max memory 8,192 MB

Graphics

Integrated Graphic Information
GPU HD Graphics 500
Device ID 0x5A85
Execution Units 12
Displays 3
Frequency 250 MHz
0.25 GHz
250,000 KHz
Max frequency 750 MHz
0.75 GHz
750,000 KHz
Max memory 8 GB
"GB" is not declared as a valid unit of measurement for this property.
Output DisplayPort, Embedded DisplayPort, HDMI, DSI
DirectX 12
OpenGL 4.3
OpenCL 1.2
OpenGL ES 3.0
HDMI 1.4b
DP 1.2
eDP 1.3
Max HDMI Res 3840x2160 @30 Hz
Max DSI Res 2560x1600 @60 Hz
Max DP Res 4096x2160 @60 Hz
Max eDP Res 3840x2160 @60 Hz
Intel Quick Sync Video
Intel Clear Video
  • Video decode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, MPEG2, VC-1, WMV9, JPEG/MJPEG.
  • Video encode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, JPEG/MJPEG.

Expansions

Template:mpu expansions

  • 2x USB 2.0 ports
  • 6x USB 3.0 ports
    • 1x USB Dual Role
    • 1x Dedicated Port
    • 3x multiplexed with PCIe 2.0
    • 1x multiplexed with SATA 3.0

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/j3455&oldid=24143"
Facts about "Celeron J3455 - Intel"
RDF feed
device id0x5A85 +
has featureintegrated gpu +
integrated gpuHD Graphics 500 +
integrated gpu base frequency250 MHz (0.25 GHz, 250,000 KHz) +
integrated gpu max frequency750 MHz (0.75 GHz, 750,000 KHz) +
l1d$ description6-way set associative +
l1i$ description8-way set associative +
l2$ description16-way set associative +
l3$ descriptionNo L3$ +