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Difference between revisions of "amd/duron/d800aut1b"
< amd‎ | duron

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'''Duron 800''' based on the Spitfire core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2000. This model was part of the first series of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} (a {{amd|Thunderbird}}-derivative) on a [[180 nm process]], this MPU operated at 800 MHz with a bus capable of 200 MT/s with a typical TDP of 35.4 W.
 
'''Duron 800''' based on the Spitfire core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2000. This model was part of the first series of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} (a {{amd|Thunderbird}}-derivative) on a [[180 nm process]], this MPU operated at 800 MHz with a bus capable of 200 MT/s with a typical TDP of 35.4 W.
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== Cache ==
 +
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
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{{cache info
 +
|l1i cache=64 KB
 +
|l1i break=1x64 KB
 +
|l1i desc=2-way set associative
 +
|l1i extra=
 +
|l1d cache=64 KB
 +
|l1d break=1x64 KB
 +
|l1d desc=2-way set associative
 +
|l1d extra=
 +
|l2 cache=64 KB
 +
|l2 break=1x64 KB
 +
|l2 desc=16-way set associative
 +
|l2 extra=
 +
|l3 cache=
 +
|l3 break=
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|l3 desc=
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|l3 extra=
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}}
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 +
== Graphics ==
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This SoC has no integrated graphics processing unit.
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 +
== Features ==
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{{mpu features
 +
| em64t      =
 +
| nx          =
 +
| txt        =
 +
| tsx        =
 +
| vpro        =
 +
| ht          =
 +
| tbt1        =
 +
| tbt2        =
 +
| bpt        =
 +
| vt-x        =
 +
| vt-d        =
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| ept        =
 +
| mmx        = Yes
 +
| emmx        = Yes
 +
| 3dnow      = Yes
 +
| e3dnow      = Yes
 +
| sse        =
 +
| sse2        =
 +
| sse3        =
 +
| ssse3      =
 +
| sse4        =
 +
| sse4.1      =
 +
| sse4.2      =
 +
| aes        =
 +
| pclmul      =
 +
| avx        =
 +
| avx2        =
 +
| bmi        =
 +
| bmi1        =
 +
| bmi2        =
 +
| f16c        =
 +
| fma3        =
 +
| mpx        =
 +
| sgx        =
 +
| eist        =
 +
}}
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* [[has feature::Halt State]]
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* [[has feature::Sleep State]]

Revision as of 23:08, 22 August 2016

Template:mpu Duron 800 based on the Spitfire core was a 32-bit x86 microprocessor developed by AMD and introduced in 2000. This model was part of the first series of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 800 MHz with a bus capable of 200 MT/s with a typical TDP of 35.4 W.

Cache

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x64 KB 2-way set associative
L1D$ 64 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x64 KB 2-way set associative
L2$ 64 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x64 KB 16-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Halt State
  • Sleep State
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/duron/d800aut1b&oldid=23700"
Facts about "Duron 800 (Spitfire) - AMD"
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has featureHalt State + and Sleep State +
l1d$ description2-way set associative +
l1i$ description2-way set associative +
l2$ description16-way set associative +