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Difference between revisions of "mathstar/arrix"
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== Architecture ==
 
== Architecture ==
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{{main|field-programmable object array}}
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Arrix is a family of [[field-programmable object array]] (FPOA). The chips can operate, depending on model, from 400 MHz to 1 GHz. At the time their performance exceeded similar budget [[FPGA]]s. Arrix are a grid of 400 logic objects. Additionally the chips also feature:
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* 2x Bi-directional 500MHz DDR 16-bit LVDS ports
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* 96x GPIO (synchronously or asynchronously at up to 100 MHz)
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* 12x banks of 500MHz internal SRAM memory banks
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* 2x 266 MHz 36-bit DDR (72-bits per cycle) RLDRAM II controllers
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The chips are arranged as a grid of 400 logic objects made up of:
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* 256x [[arithmetic logic unit|ALU]]
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** 16 bit data, 5 bits control, 32 operations
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** {{arch|16}} add/sub/shift/rotate/AND/OR/XOR
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** circuitry for cascading status bits for making larger word
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* 80x [[register file|RFs]]
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** 128 Byte, dualport RAM or FIFO
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* 64x [[multiply accumulator|MAC]]x
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** 16x16 single clock cycle [[multiplier]]
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** 32 bit intermediate result, signed or unsigned
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** 40 bit [[accumulator]], 256 accumulations before [[overflow]]
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* 12x Internal [[RAM]] banks
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** 768 x 76 bits
  
 
== Members ==
 
== Members ==

Revision as of 23:00, 27 June 2016

Arrix
arrix chip.gif
Developer MathStar
Manufacturer TSMC
Type Programmable logic device
Introduction September 25, 2006 (announced)
November 29, 2006 (launch)
Production 2006-2009
Word size 16 bit
2 octets
4 nibbles
Process 130 nm
0.13 μm
1.3e-4 mm
, 90 nm
0.09 μm
9.0e-5 mm
, 65 nm
0.065 μm
6.5e-5 mm
, 45 nm
0.045 μm
4.5e-5 mm
Technology CMOS
Clock 400 MHz-1,000 MHz
Package FCBGA-896
Socket FCBGA-896
Succession
←
Builder

Arrix was a family of field-programmable object array designed by MathStar and introduced in late 2006. MathStar continued manufacturing this until 2009.

Architecture

Main article: field-programmable object array

Arrix is a family of field-programmable object array (FPOA). The chips can operate, depending on model, from 400 MHz to 1 GHz. At the time their performance exceeded similar budget FPGAs. Arrix are a grid of 400 logic objects. Additionally the chips also feature:

  • 2x Bi-directional 500MHz DDR 16-bit LVDS ports
  • 96x GPIO (synchronously or asynchronously at up to 100 MHz)
  • 12x banks of 500MHz internal SRAM memory banks
  • 2x 266 MHz 36-bit DDR (72-bits per cycle) RLDRAM II controllers

The chips are arranged as a grid of 400 logic objects made up of:

  • 256x ALU
    • 16 bit data, 5 bits control, 32 operations
    • 16-bit add/sub/shift/rotate/AND/OR/XOR
    • circuitry for cascading status bits for making larger word
  • 80x RFs
    • 128 Byte, dualport RAM or FIFO
  • 64x MACx
  • 12x Internal RAM banks
    • 768 x 76 bits

Members

MOA2400D Series

Model Frequency OBjects Package Temp Range
MOA2400D-10 1,000 MHz 400 FCBGA-896 Commercial
MOA2400D-10R 1,000 MHz 400 FCBGA-896 RoHS Commercial
MOA2400D-09 900 MHz 400 FCBGA-896 Industrial
MOA2400D-09R 900 MHz 400 FCBGA-896 RoHS Industrial
MOA2400D-08 800 MHz 400 FCBGA-896 Industrial
MOA2400D-08R 800 MHz 400 FCBGA-896 RoHS Industrial
MOA2400D-06 600 MHz 400 FCBGA-896 Industrial
MOA2400D-06R 600 MHz 400 FCBGA-896 RoHS Industrial
MOA2400D-04 400 MHz 400 FCBGA-896 Commercial
MOA2400D-04R 400 MHz 400 FCBGA-896 RoHS Commercial

Documents

Product Brief

IP Cores

Software

Retrieved from "https://en.wikichip.org/w/index.php?title=mathstar/arrix&oldid=22508"
Facts about "Arrix - MathStar"
RDF feed
designerMathStar +
first announcedSeptember 25, 2006 +
first launchedNovember 29, 2006 +
full page namemathstar/arrix +
instance ofintegrated circuit family +
main designerMathStar +
manufacturerTSMC +
nameArrix +
packageFCBGA-896 +
process130 nm (0.13 μm, 1.3e-4 mm) +, 90 nm (0.09 μm, 9.0e-5 mm) +, 65 nm (0.065 μm, 6.5e-5 mm) + and 45 nm (0.045 μm, 4.5e-5 mm) +
socketFCBGA-896 +
technologyCMOS +
word size16 bit (2 octets, 4 nibbles) +