Semiconductor & Computer Engineering
| Line 38: | Line 38: | ||
| die size = | | die size = | ||
| word size = 32 bit | | word size = 32 bit | ||
| − | | core count = | + | | core count = 344 |
| thread count = | | thread count = | ||
| max cpus = | | max cpus = | ||
| Line 73: | Line 73: | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
}} | }} | ||
| − | '''Am2045''' (later renamed '''Am2045A'''), codename '''[[codename::Kestrel]]''', was [[Ambric]]'s original flagship [[MPPA]] introduced in late 2006. This model was made of {{ambric|am2000#Architecture| | + | '''Am2045''' (later renamed '''Am2045A'''), codename '''[[codename::Kestrel]]''', was [[Ambric]]'s original flagship [[MPPA]] introduced in late 2006. This model was made of {{ambric|am2000#Architecture|43 Brics}} arranged as a grid of about 5x9, making up a total of 344 {{arch|32}} [[RICS]]-like cores operating asynchronously at 1-333 MHz. This model was later replace with {{\\|Am2045B}}. |
| − | Originally this chip was supposed to have 45 Brics, hence the '2045' which was supposed to have 360 cores. However the final model only had 42 | + | Originally this chip was supposed to have 45 Brics, hence the '2045' which was supposed to have 360 cores. However the final model only had 43 bric for 344 cores instead. Earlier models might have had only 42 brics at one point for 336 cores. |
== Architecture == | == Architecture == | ||
{{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}} | {{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}} | ||
| − | The Am2045 is made of | + | The Am2045 is made of 43 homogeneous 'Brics' laid out in a 5 by 9 grid to form 344 cores and 344 RAM units. |
General layout: | General layout: | ||
| − | * | + | * 43x Brics |
** 2x Computer Unit (CU) | ** 2x Computer Unit (CU) | ||
*** 2x SRD {{arch|32}} CPU | *** 2x SRD {{arch|32}} CPU | ||
| Line 90: | Line 90: | ||
== Cache == | == Cache == | ||
| − | The Am2045 contains | + | The Am2045 contains 43 Brics, each with its own [[RAM]] Unit (RU) of 13 kB of SRAM for a total of 559 kB of SRAM. |
== Memory controller == | == Memory controller == | ||
Revision as of 08:40, 26 June 2016
Template:mpu Am2045 (later renamed Am2045A), codename Kestrel, was Ambric's original flagship MPPA introduced in late 2006. This model was made of 43 Brics arranged as a grid of about 5x9, making up a total of 344 32-bit RICS-like cores operating asynchronously at 1-333 MHz. This model was later replace with Am2045B.
Originally this chip was supposed to have 45 Brics, hence the '2045' which was supposed to have 360 cores. However the final model only had 43 bric for 344 cores instead. Earlier models might have had only 42 brics at one point for 336 cores.
Architecture
- Main article: Am2000 § Architecture
The Am2045 is made of 43 homogeneous 'Brics' laid out in a 5 by 9 grid to form 344 cores and 344 RAM units.
General layout:
- 43x Brics
Cache
The Am2045 contains 43 Brics, each with its own RAM Unit (RU) of 13 kB of SRAM for a total of 559 kB of SRAM.
Memory controller
| Integrated Memory Controller | |
| Type | DDR2-400 |
| Controllers | 2 |
| Channels | 1 |
| Max memory | 4 GB |
Expansions
- PCIe
- JTAG
- 128x GPIO @ 100 MHz
- serial flash
Die Shot
 |
.png)
|
| codename | Kestrel + |
| has feature | PCIe +, JTAG +, GPIO + and serial flash + |