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Difference between revisions of "intel/xeon e7/e7-2803"
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| − | '''Xeon E7-2803''' is a {{arch|64}} [[x86]] data center microprocessor that supports up to 2 sockets. This first generation ({{intel|Westmere|Westmere}}-based) {{intel|Xeon E7}} processor operates at 1.73 GHz with a TDP of 105 W but does not support {{intel|turbo boost technology}}. This processor supports up to 4 channels of DDR3, supporting up to 1 TB of memory. | + | '''Xeon E7-2803''' is a {{arch|64}} hexa-core [[x86]] data center microprocessor that supports up to 2 sockets. This first generation ({{intel|Westmere|Westmere}}-based) {{intel|Xeon E7}} processor operates at 1.73 GHz with a TDP of 105 W but does not support {{intel|turbo boost technology}}. This processor supports up to 4 channels of DDR3, supporting up to 1 TB of memory. |
| + | |||
| + | == Cache == | ||
| + | {{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | ||
| + | {{cache info | ||
| + | |l1i cache=192 KB | ||
| + | |l1i break=6x32 KB | ||
| + | |l1i desc=4-way set associative | ||
| + | |l1i extra=(per core) | ||
| + | |l1d cache=192 KB | ||
| + | |l1d break=6x32 KB | ||
| + | |l1d desc=8-way set associative | ||
| + | |l1d extra=(per core) | ||
| + | |l2 cache=1.5 MB | ||
| + | |l2 break=6x256 KB | ||
| + | |l2 desc=8-way set associative | ||
| + | |l2 extra=(per core) | ||
| + | |l3 cache=18 MB | ||
| + | |l3 break= | ||
| + | |l3 desc=16-way set associative | ||
| + | |l3 extra= | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This SoC has no integrated graphics processing unit. | ||
| + | |||
| + | == Memory controller == | ||
| + | {{integrated memory controller | ||
| + | | type = DDR3-800 | ||
| + | | controllers = 1 | ||
| + | | channels = 4 | ||
| + | | ecc support = Yes | ||
| + | | max bandwidth = | ||
| + | | bandwidth schan = | ||
| + | | bandwidth dchan = | ||
| + | | max memory = 1024 GB | ||
| + | }} | ||
| + | |||
| + | == Features == | ||
| + | {{mpu features | ||
| + | | em64t = Yes | ||
| + | | nx = Yes | ||
| + | | txt = Yes | ||
| + | | tsx = | ||
| + | | vpro = | ||
| + | | ht = Yes | ||
| + | | tbt1 = | ||
| + | | tbt2 = | ||
| + | | bpt = | ||
| + | | vt-x = Yes | ||
| + | | vt-d = yes | ||
| + | | ept = Yes | ||
| + | | mmx = Yes | ||
| + | | sse = Yes | ||
| + | | sse2 = Yes | ||
| + | | sse3 = Yes | ||
| + | | ssse3 = Yes | ||
| + | | sse4.1 = Yes | ||
| + | | sse4.2 = Yes | ||
| + | | aes = Yes | ||
| + | | pclmul = | ||
| + | | avx = | ||
| + | | avx2 = | ||
| + | | bmi = | ||
| + | | bmi1 = | ||
| + | | bmi2 = | ||
| + | | f16c = | ||
| + | | fma3 = | ||
| + | | mpx = | ||
| + | | sgx = | ||
| + | | eist = Yes | ||
| + | | secure key = | ||
| + | | os guard = | ||
| + | | intel at = | ||
| + | }} | ||
Revision as of 23:01, 12 June 2016
Template:mpu Xeon E7-2803 is a 64-bit hexa-core x86 data center microprocessor that supports up to 2 sockets. This first generation (Westmere-based) Xeon E7 processor operates at 1.73 GHz with a TDP of 105 W but does not support turbo boost technology. This processor supports up to 4 channels of DDR3, supporting up to 1 TB of memory.
Contents
Cache
- Main article: Westmere § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 192 KB "KB" is not declared as a valid unit of measurement for this property. |
6x32 KB 4-way set associative (per core) |
| L1D$ | 192 KB "KB" is not declared as a valid unit of measurement for this property. |
6x32 KB 8-way set associative (per core) |
| L2$ | 1.5 MB "MB" is not declared as a valid unit of measurement for this property. |
6x256 KB 8-way set associative (per core) |
| L3$ | 18 MB "MB" is not declared as a valid unit of measurement for this property. |
16-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR3-800 |
| Controllers | 1 |
| Channels | 4 |
| ECC Support | Yes |
| Max memory | 1024 GB |
Features
Facts about "Xeon E7-2803 - Intel"
| l1d$ description | 8-way set associative + |
| l1i$ description | 4-way set associative + |
| l2$ description | 8-way set associative + |
| l3$ description | 16-way set associative + |