From WikiChip
Difference between revisions of "amd/am486/am486dx2-100v8t"
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| bus type = FSB | | bus type = FSB | ||
| bus speed = 50 MHz | | bus speed = 50 MHz | ||
− | | bus rate = | + | | bus rate = 50 MT/s |
| clock multiplier = 2 | | clock multiplier = 2 | ||
| cpuid = | | cpuid = |
Revision as of 04:38, 17 May 2016
Template:mpu Am486DX2-100V8T was an 80486-compatible microprocessor introduced by AMD in 1994. This processor had a clock multiplier of 2 having base frequency of 100 MHz with a bus frequency of 50 MHz. This model is essentially identical to Am486DX2-100. The new model name was used to differentiate it from the Am486DX2-100V8B which is a similar model with a Write-Back cache policy. The Am486DX2-100V16B is also similar models with double the cache size.
Cache
- Main article: 80486 § Cache
Cache Info [Edit Values] | ||
L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.