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Difference between revisions of "amd/am486/am486dx4-100v16b"
< amd‎ | am486

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| socket 0 3          = Socket 3
 
| socket 0 3          = Socket 3
 
| socket 0 3 type    =  
 
| socket 0 3 type    =  
 +
| package 1          = SQFP-208
 +
| package 1 type      = SQFP
 +
| package 1 pins      = 208
 +
| package 1 pitch    = 0.5 mm
 +
| package 1 width    = 30.35 mm
 +
| package 1 length    = 30.35 mm
 +
| package 1 height    = 3.8 mm
 +
| socket 1            =
 +
| socket 1 type      =
 
}}
 
}}
 
'''Am486DX2-66V16B''' was an Enhanced {{amd|Am486}} microprocessor introduced by [[AMD]] in 1997. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model had larger L1 cache of 16 KB with Write-Back policy. This model has twice as much cache as the {{\\|Am486DX4-100V8T}} model (previously {{\\|Am486DX4-100}}). This "Enhanced" Am486 includes some other features such as SMM.
 
'''Am486DX2-66V16B''' was an Enhanced {{amd|Am486}} microprocessor introduced by [[AMD]] in 1997. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model had larger L1 cache of 16 KB with Write-Back policy. This model has twice as much cache as the {{\\|Am486DX4-100V8T}} model (previously {{\\|Am486DX4-100}}). This "Enhanced" Am486 includes some other features such as SMM.

Revision as of 22:30, 16 May 2016

Template:mpu Am486DX2-66V16B was an Enhanced Am486 microprocessor introduced by AMD in 1997. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model had larger L1 cache of 16 KB with Write-Back policy. This model has twice as much cache as the Am486DX4-100V8T model (previously Am486DX4-100). This "Enhanced" Am486 includes some other features such as SMM.

Cache

Main article: 80486 § Cache
Cache Info [Edit Values]
L1$ 16 KB
"KB" is not declared as a valid unit of measurement for this property.
1x16 KB 4-way set associative (unified, write-back policy)

Graphics

This chip had no integrated graphics processing unit.

Features

  • System Management Mode (SMM)

See also

has featureSystem Management Mode +
l1$ description4-way set associative +