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Difference between revisions of "amd/am486/am486dx2-100v16b"
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| packaging = Yes | | packaging = Yes | ||
| − | | package | + | | package 0 = CPGA-168 |
| − | | package type | + | | package 0 type = CPGA |
| − | | package pitch | + | | package 0 pins = 168 |
| − | | package | + | | package 0 pitch = 2.286 mm |
| − | | socket | + | | package 0 width = 44.069 mm |
| − | | socket 2 | + | | package 0 length = 44.069 mm |
| − | | socket 3 | + | | package 0 height = 3.556 mm |
| + | | socket 0 = Socket 1 | ||
| + | | socket 0 type = | ||
| + | | socket 0 2 = Socket 2 | ||
| + | | socket 0 2 type = | ||
| + | | socket 0 3 = Socket 3 | ||
| + | | socket 0 3 type = | ||
}} | }} | ||
'''Am486DX2-100V16B''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1995. This processor had a clock multiplier of 2 having base frequency of 100 MHz with a bus frequency of 50 MHz. This model had a write-back cache and double the size of L1 of previous models (16 KB). The {{\\|Am486DX2-100V8T}} and {{\\|Am486DX2-100V8B}} are an 8 KB version of this model. | '''Am486DX2-100V16B''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1995. This processor had a clock multiplier of 2 having base frequency of 100 MHz with a bus frequency of 50 MHz. This model had a write-back cache and double the size of L1 of previous models (16 KB). The {{\\|Am486DX2-100V8T}} and {{\\|Am486DX2-100V8B}} are an 8 KB version of this model. | ||
Revision as of 21:36, 16 May 2016
Template:mpu Am486DX2-100V16B was an 80486-compatible microprocessor introduced by AMD in 1995. This processor had a clock multiplier of 2 having base frequency of 100 MHz with a bus frequency of 50 MHz. This model had a write-back cache and double the size of L1 of previous models (16 KB). The Am486DX2-100V8T and Am486DX2-100V8B are an 8 KB version of this model.
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 16 KB "KB" is not declared as a valid unit of measurement for this property. |
1x16 KB 4-way set associative (unified, write-back policy) |
Graphics
This chip had no integrated graphics processing unit.