Semiconductor & Computer Engineering
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Difference between revisions of "amd/am486/am486dx2-50"
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| core stepping 2 = | | core stepping 2 = | ||
| process = 700 nm | | process = 700 nm | ||
| − | | process | + | | process 2 = 500 nm |
| transistors = 1,200,000 | | transistors = 1,200,000 | ||
| technology = CMOS | | technology = CMOS | ||
Revision as of 02:48, 15 May 2016
Template:mpu Am486DX2-50 was an 80486-compatible microprocessor introduced by AMD in 1993. This processor had a clock multiplier of 2 having base frequency of 50 MHz with a FSB frequency of 25 MHz.
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.