Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/80486/486dx4-100"
(→Gallery) |
(→Gallery) |
||
| Line 105: | Line 105: | ||
Ic-photo-Intel--A80486DX4100-(486DX4-CPU).png|A80486DX4100, S-Spec SK096 | Ic-photo-Intel--A80486DX4100-(486DX4-CPU).png|A80486DX4100, S-Spec SK096 | ||
Ic-photo-intel-A80486DX4100-(486DX4).png|A80486DX4100, S-Spec SK096 | Ic-photo-intel-A80486DX4100-(486DX4).png|A80486DX4100, S-Spec SK096 | ||
| + | File:Intel DX4 microprocessor.jpg|A80486DX4100, S-Spec SK096 | ||
</gallery> | </gallery> | ||
== See also == | == See also == | ||
* {{intel|80486|80486 family}} | * {{intel|80486|80486 family}} | ||
Revision as of 16:16, 11 May 2016
Template:mpu i486DX4-100 was a fourth-generation x86 microprocessor introduced by Intel in 1994. This chip, which is based on the 80486 microarchitecture, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 100 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM). The DX4 series had twice as much cache space as the older processors.
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 16 KB "KB" is not declared as a valid unit of measurement for this property. |
1x16 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
Gallery
A80486DX4100, S-Spec SK096
A80486DX4100, S-Spec SK096
A80486DX4100, S-Spec SK096
.png)
.png)
