Semiconductor & Computer Engineering
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Difference between revisions of "intel/80486/486sl-25"
| Line 24: | Line 24: | ||
| bus rate = 25 MT/s | | bus rate = 25 MT/s | ||
| clock multiplier = 1 | | clock multiplier = 1 | ||
| − | | s-spec = | + | | s-spec = SX709 |
| + | | s-spec 2 = SX741 | ||
| + | | s-spec 3 = SX745 | ||
| + | | s-spec 4 = SX804 | ||
| + | | s-spec 5 = SX806 | ||
| s-spec es = | | s-spec es = | ||
| s-spec qs = | | s-spec qs = | ||
| Line 46: | Line 50: | ||
| electrical = Yes | | electrical = Yes | ||
| − | | power = | + | | power = 0.94 W |
| − | | v core = | + | | v core = 3.3 V |
| − | | v core tolerance = | + | | v core tolerance = 0.3 V |
| − | |||
| − | |||
| temp max = 85 °C | | temp max = 85 °C | ||
| temp min = 0 °C | | temp min = 0 °C | ||
| packaging = Yes | | packaging = Yes | ||
| − | | package = | + | | package = QFP-196 |
| − | | package type = | + | | package type = QFP |
| package size = | | package size = | ||
| socket = | | socket = | ||
Revision as of 15:44, 11 May 2016
Template:mpu i486SL-25 was a fourth-generation x86 microprocessor introduced by Intel in 1992. This chip, which is based on the 80486 microarchitecture, operated at 25 MHz. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM). This series was designed to be a low power version of the i486DX, offering lower voltage and power saving features for portable mobile computers.
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)