Semiconductor & Computer Engineering
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Difference between revisions of "intel/80486/486dx4-100"
| Line 38: | Line 38: | ||
| s-spec 6 = SX900 | | s-spec 6 = SX900 | ||
| s-spec 7 = SX908 | | s-spec 7 = SX908 | ||
| + | | s-spec 8 = SK053 | ||
| + | | s-spec 9 = SK063 | ||
| + | | s-spec 10 = SK099 | ||
| + | | s-spec 11 = SL2M9 | ||
| + | | s-spec 12 = SX876 | ||
| + | | s-spec 13 = SX906 | ||
| s-spec es = | | s-spec es = | ||
| s-spec qs = Q0746 | | s-spec qs = Q0746 | ||
| + | | s-spec qs = Q0747 | ||
| + | | s-spec qs = Q860 | ||
| cpuid = 480 | | cpuid = 480 | ||
| cpuid = 483 | | cpuid = 483 | ||
Revision as of 15:42, 11 May 2016
Template:mpu i486DX4-100 was a fourth-generation x86 microprocessor introduced by Intel in 1994. This chip, which is based on the 80486 microarchitecture, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 100 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM). The DX4 series had twice as much cache space as the older processors.
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 16 KB "KB" is not declared as a valid unit of measurement for this property. |
1x16 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)