From WikiChip
Difference between revisions of "intel/80486/486dx-50"
Line 24: | Line 24: | ||
| bus rate = 50 MT/s | | bus rate = 50 MT/s | ||
| clock multiplier = 1 | | clock multiplier = 1 | ||
− | | s-spec = | + | | s-spec = SX408 |
+ | | s-spec 2 = SX409 | ||
+ | | s-spec 3 = SX518 | ||
+ | | s-spec 4 = SX546 | ||
+ | | s-spec 5 = SX547 | ||
+ | | s-spec 6 = SX705 | ||
+ | | s-spec 7 = SX710 | ||
+ | | s-spec 8 = SXE69 | ||
| s-spec es = | | s-spec es = | ||
− | | s-spec qs = | + | | s-spec qs = Q0209 |
− | | cpuid = | + | | s-spec qs 2 = Q302 |
+ | | cpuid = 411 | ||
+ | | cpuid 2 = 413 | ||
| microarch = 80486 | | microarch = 80486 | ||
Line 47: | Line 56: | ||
| electrical = Yes | | electrical = Yes | ||
− | | power = | + | | power = 4 W |
| v core = 5 V | | v core = 5 V | ||
− | | v core tolerance = | + | | v core tolerance = 5% |
| temp max = 85 °C | | temp max = 85 °C | ||
| temp min = 0 °C | | temp min = 0 °C |
Revision as of 15:29, 11 May 2016
Template:mpu i486DX-50 was a fourth-generation x86 microprocessor introduced by Intel in 1991. This chip, which is based on the 80486 microarchitecture, operated at 50 MHz. This chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).
Contents
Cache
- Main article: 80486 § Cache
Cache Info [Edit Values] | ||
L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy ) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)