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Difference between revisions of "intel/xeon d/d-1571"
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{{soc networking | {{soc networking | ||
| SFI interface = Yes | | SFI interface = Yes | ||
− | | KR interface = | + | | KR interface = Yes |
− | | KR4 | + | | KR4 interface = No |
− | | KX | + | | KX interface = Yes |
− | | KX4 | + | | KX4 interface = No |
| 10Base-T = No | | 10Base-T = No | ||
| 100Base-T = No | | 100Base-T = No |
Revision as of 15:03, 7 May 2016
Template:mpu The Xeon D-1571 is a 64-bit hexadeca-core x86-64 microserver SoC that was introduced by Intel in February of 2016. The D-1571 operates at 1.3 GHz with a turbo frequency of 2.1 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).
Cache
- Main article: Broadwell's Cache
Cache Info [Edit Values] | ||
L1I$ | 512 KB "KB" is not declared as a valid unit of measurement for this property. |
16x32 KB 8-way set associative (per core) |
L1D$ | 512 KB "KB" is not declared as a valid unit of measurement for this property. |
16x32 KB 8-way set associative (per core) |
L2$ | 4 MB "MB" is not declared as a valid unit of measurement for this property. |
16x256 KB 8-way set associative (per core) |
L3$ | 24 MB "MB" is not declared as a valid unit of measurement for this property. |
16x1.5 MB (per core) |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133 |
Controllers | 1 |
Channels | 2 |
ECC Support | Yes |
Max memory | 128 GB |
Expansions
Networking
Networking | |
SFI interface | Yes |
KR interface | Yes |
KR4 interface | No |
KX interface | Yes |
KX4 interface | No |
10Base-T | No |
100Base-T | No |
1000Base-T | Yes |
10GBase-T | Yes |
Features
Facts about "Xeon D-1571 - Intel"
l1d$ description | 8-way set associative + |
l1i$ description | 8-way set associative + |
l2$ description | 8-way set associative + |