Revision as of 20:31, 12 April 2016

Code

{{microarchitecture
| name          = 
| manufacturer  = 
| introduction  = 
| phase-out     =
| process       = 
| cores         = 
| cores 2       = 
| cores N       = 

| pipeline      = <!-- yes for following options -->
| type          = <!-- e.g. "Superscalar" -->
| type 2        = 
| type N        = 
| OoOE          = <!-- Yes or No only -->
| speculative   = <!-- Yes or No only -->
| renaming      = <!-- Yes or No only -->
| isa           = 
| isa 2         = 
| isa N         = 
| stages        = <!-- ONLY IF FIXED SIZE, otherwise use below for range -->
| stages min    =
| stages max    =
| issues        = 

| inst          = <!-- yes for instructions options -->
| feature       = 
| extension     = 
| extension 2   = 
| extension N   = 

| cache         = <!-- yes for cache info -->
| l1i           =
| l1i per       =
| l1i desc      =
| l1d           = 
| l1d per       = 
| l1d desc      =
| l2            = 
| l2 per        = 
| l2 desc       = 
| l3            = 
| l3 per        = 
| l3 desc       = 

| core names       = <!-- Yes if specify -->
| core name        =
| core name 2      =
| core name N      =

| succession       = <!-- yes for succession info -->
| predecessor      =
| predecessor link =
| successor        =
| successor link   =
}}