Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/xeon d/d-1518"
| Line 62: | Line 62: | ||
| socket = BGA1667 | | socket = BGA1667 | ||
| socket type = BGA | | socket type = BGA | ||
| + | }} | ||
| + | |||
| + | == Cache == | ||
| + | {{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell's Cache}} | ||
| + | {{cache info | ||
| + | |l1i cache=128 KB | ||
| + | |l1i break=4x32 KB | ||
| + | |l1i desc=8-way set associative | ||
| + | |l1i extra=(per core) | ||
| + | |l1d cache=128 KB | ||
| + | |l1d break=4x32 KB | ||
| + | |l1d desc=8-way set associative | ||
| + | |l1d extra=(per core) | ||
| + | |l2 cache=1 MB | ||
| + | |l2 break=4x256 KB | ||
| + | |l2 desc=8-way set associative | ||
| + | |l2 extra=(per core) | ||
| + | |l3 cache=6 MB | ||
| + | |l3 desc= | ||
| + | |l3 extra=(shared) | ||
}} | }} | ||
Revision as of 21:49, 11 April 2016
Cache
- Main article: Broadwell's Cache
| Cache Info [Edit Values] | ||
| L1I$ | 128 KB "KB" is not declared as a valid unit of measurement for this property. |
4x32 KB 8-way set associative (per core) |
| L1D$ | 128 KB "KB" is not declared as a valid unit of measurement for this property. |
4x32 KB 8-way set associative (per core) |
| L2$ | 1 MB "MB" is not declared as a valid unit of measurement for this property. |
4x256 KB 8-way set associative (per core) |
| L3$ | 6 MB "MB" is not declared as a valid unit of measurement for this property. |
(shared) |
Facts about "Xeon D-1518 - Intel"
| l1d$ description | 8-way set associative + |
| l1i$ description | 8-way set associative + |
| l2$ description | 8-way set associative + |