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Difference between revisions of "arm holdings/microarchitectures/arm11"
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'''ARM11 MPCore''' | '''ARM11 MPCore''' | ||
* [[Intel]] | * [[Intel]] | ||
| − | |||
* [[NEC]] | * [[NEC]] | ||
| − | * [[ | + | * [[NVIDIA]] |
* [[Netronome]] | * [[Netronome]] | ||
| − | + | * [[PMC Sierra]] | |
| − | * [[PMC | ||
| − | |||
* [[Renesas]] | * [[Renesas]] | ||
* [[Sarnoff]] | * [[Sarnoff]] | ||
'''ARM1176JZ(F)-S''' | '''ARM1176JZ(F)-S''' | ||
* [[Broadcom]] | * [[Broadcom]] | ||
| − | |||
* [[Infineon]] | * [[Infineon]] | ||
| − | |||
| − | |||
* [[Matsushita]] | * [[Matsushita]] | ||
* [[NEC]] | * [[NEC]] | ||
| − | * [[ | + | * [[NXP]] |
| − | * [[ | + | * [[Renesas]] |
* [[Sunplus]] | * [[Sunplus]] | ||
| − | * [[Texas | + | * [[Texas Instruments]] |
| − | |||
* [[Toshiba]] | * [[Toshiba]] | ||
'''ARM1156T2(F)-S''' | '''ARM1156T2(F)-S''' | ||
* [[Comsys]] | * [[Comsys]] | ||
| − | * [[LSI | + | * [[LSI Logic]] |
| − | |||
* [[NEC]] | * [[NEC]] | ||
| − | |||
'''ARM1136J(F)-S''': | '''ARM1136J(F)-S''': | ||
* [[Accent]] | * [[Accent]] | ||
* [[Broadcom]] | * [[Broadcom]] | ||
| − | |||
* [[Ceroma]] | * [[Ceroma]] | ||
* [[eSilicon]] | * [[eSilicon]] | ||
| − | |||
* [[Freescale]] | * [[Freescale]] | ||
| − | + | * [[LSI Logic]] | |
| − | * [[LSI]] | + | |
| − | |||
* [[Matsushita]] | * [[Matsushita]] | ||
* [[Mindspeed]] | * [[Mindspeed]] | ||
* [[NEC]] | * [[NEC]] | ||
| − | |||
* [[Qualcomm]] | * [[Qualcomm]] | ||
* [[Renesas]] | * [[Renesas]] | ||
| − | * [[STMicroelectronics]] | + | * [[STMicroelectronics|STMicro]] |
| − | * [[Texas | + | |
| − | + | * [[Texas Instruments]] | |
* [[Toshiba]] | * [[Toshiba]] | ||
}} | }} | ||
| + | |||
| + | == Die == | ||
| + | * [[0.35 μm process]] | ||
| + | * 5.55 mm² die size (with cache) | ||
| + | * 2.85 mm² die size (without cache) | ||
| + | * 333-550 MHz max frequency | ||
| + | * 0.8 mW/MHz with cache | ||
| + | * 0.6 mW/MHz without cache | ||
Latest revision as of 13:55, 11 October 2025
| Edit Values | |
| ARM11 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | April 29, 2002 |
| Succession | |
ARM11 is the successor to the ARM10, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as an IP core and is sold to other semiconductor companies to be implemented in their own chips. The ARM11 was designed by the Arm Sophia-Antipolis design center.
Contents
Architecture[edit]
Key changes from ARM10[edit]
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This section is empty; you can help add the missing info by editing this page. |
Block Diagram[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy[edit]
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This section is empty; you can help add the missing info by editing this page. |
Licensees[edit]
In 2013 Arm reported 82 licensees. The following were named.
ARM11 MPCore
ARM1176JZ(F)-S
ARM1156T2(F)-S
ARM1136J(F)-S:
Die[edit]
- 0.35 μm process
- 5.55 mm² die size (with cache)
- 2.85 mm² die size (without cache)
- 333-550 MHz max frequency
- 0.8 mW/MHz with cache
- 0.6 mW/MHz without cache
Facts about "ARM11 - Microarchitectures - ARM"
| codename | ARM11 + |
| designer | ARM Holdings + |
| first launched | April 29, 2002 + |
| full page name | arm holdings/microarchitectures/arm11 + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | ARM11 + |