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Difference between revisions of "mediatek/helio/p30"
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{{mediatek title|Helio P30}} | {{mediatek title|Helio P30}} | ||
{{chip | {{chip | ||
− | |||
|name=Helio P30 | |name=Helio P30 | ||
|image=helio p30.png | |image=helio p30.png | ||
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|designer 2=ARM Holdings | |designer 2=ARM Holdings | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
− | |model number=P30 | + | |model number=Helio P30 |
+ | |part number=MT6758 | ||
|market=Mobile | |market=Mobile | ||
|first announced=August 28, 2017 | |first announced=August 28, 2017 | ||
+ | |first launched=Aug 28, 2017 | ||
|family=Helio | |family=Helio | ||
|series=Helio P | |series=Helio P | ||
− | |frequency=1 | + | |frequency=1.65 GHz |
− | |frequency 2=2 | + | |frequency 2=2.3 GHz |
|isa=ARMv8 | |isa=ARMv8 | ||
|isa family=ARM | |isa family=ARM | ||
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'''Helio P30''' is a mid-range performance {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] set to launch in late [[2017]]. This SoC, which is fabricated on [[TSMC]]'s [[16 nm process]], incorporates eight {{armh|Cortex-A53|l=arch}} cores with four [[little cores]] operating at up to 1.65 GHz and four [[big cores]] operating at up to 2.3 GHz. The Helio P30 supports up to 6 GiB of dual-channel LPDDR4X-3200 memory and incorporates a modem supporting [[LTE]] User Equipment (UE) category 7 (DL)/13 (UL). | '''Helio P30''' is a mid-range performance {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] set to launch in late [[2017]]. This SoC, which is fabricated on [[TSMC]]'s [[16 nm process]], incorporates eight {{armh|Cortex-A53|l=arch}} cores with four [[little cores]] operating at up to 1.65 GHz and four [[big cores]] operating at up to 2.3 GHz. The Helio P30 supports up to 6 GiB of dual-channel LPDDR4X-3200 memory and incorporates a modem supporting [[LTE]] User Equipment (UE) category 7 (DL)/13 (UL). | ||
+ | == Wireless == | ||
+ | {{wireless links | ||
+ | | 4g = Yes | ||
+ | | lte a = Yes | ||
+ | | e-utran = Yes | ||
+ | | ue cat = 7 (DL), 13 (UL) | ||
+ | }} | ||
− | + | == Camera == | |
− | + | * 25MP (single), 16MP+16MP (dual) | |
+ | ** 3840 x 2160 max recording resolution @ 30 FPS | ||
+ | ** color+mono, wide+tele zoom with real-time depth engine | ||
== Cache == | == Cache == | ||
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| execution units = 2 | | execution units = 2 | ||
| frequency = 950 MHz | | frequency = 950 MHz | ||
− | |||
| output dsi = Yes | | output dsi = Yes | ||
− | |||
| max res dsi = 2160x1080 | | max res dsi = 2160x1080 | ||
− | |||
| direct3d ver = 12 | | direct3d ver = 12 | ||
| opencl ver = 2.0 | | opencl ver = 2.0 | ||
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|} | |} | ||
− | == | + | == Utilizing devices == |
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− | + | *Gionee M7 (2017) | |
− | * | + | *Gionee S11S (2017) |
− | * | + | *Coolpad Cool 10 (2020) |
− | * | + | *Xiaolajiao 小辣椒 TS8 (2020) |
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− | |||
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* [[used by::XXXXXXXXXXX]] | * [[used by::XXXXXXXXXXX]] | ||
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{{expand list}} | {{expand list}} |
Latest revision as of 04:39, 12 July 2025
Edit Values | |
Helio P30 | |
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General Info | |
Designer | MediaTek, ARM Holdings |
Manufacturer | TSMC |
Model Number | Helio P30 |
Part Number | MT6758 |
Market | Mobile |
Introduction | August 28, 2017 (announced) Aug 28, 2017 (launched) |
General Specs | |
Family | Helio |
Series | Helio P |
Frequency | 1.65 GHz, 2.3 GHz |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Cortex-A53 |
Core Name | Cortex-A53 |
Process | 16 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 6 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Helio P30 is a mid-range performance 64-bit octa-core ARM LTE system on a chip designed by MediaTek set to launch in late 2017. This SoC, which is fabricated on TSMC's 16 nm process, incorporates eight Cortex-A53 cores with four little cores operating at up to 1.65 GHz and four big cores operating at up to 2.3 GHz. The Helio P30 supports up to 6 GiB of dual-channel LPDDR4X-3200 memory and incorporates a modem supporting LTE User Equipment (UE) category 7 (DL)/13 (UL).
Wireless[edit]
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Cellular | |||||||
4G |
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Camera[edit]
- 25MP (single), 16MP+16MP (dual)
- 3840 x 2160 max recording resolution @ 30 FPS
- color+mono, wide+tele zoom with real-time depth engine
Cache[edit]
- Main article: Cortex-A53 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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This section is empty; you can help add the missing info by editing this page. |
Memory controller[edit]
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Integrated Memory Controller
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Graphics[edit]
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Integrated Graphics Information
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Hardware Accelerated Video Capabilities | ||
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Codec | Encode | Decode |
MPEG-4 AVC (H.264) | @ 30 FPS | @ 30 FPS |
HEVC (H.265) | ✘ | @ 30 FPS |
VP9 | @ 30 FPS | @ 30 FPS |
Utilizing devices[edit]
- Gionee M7 (2017)
- Gionee S11S (2017)
- Coolpad Cool 10 (2020)
- Xiaolajiao 小辣椒 TS8 (2020)
This list is incomplete; you can help by expanding it.
Facts about "Helio P30 - MediaTek"