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Difference between revisions of "intel/microarchitectures/sapphire rapids"
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|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
−
|introduction=2020
+
|introduction=2023
−
|process=10 nm
+
|process=Intel 7
 
|isa=x86-64
 
|isa=x86-64
 
|predecessor=Ice Lake (server)
 
|predecessor=Ice Lake (server)
 
|predecessor link=intel/microarchitectures/ice lake (server)
 
|predecessor link=intel/microarchitectures/ice lake (server)
−
|successor=Granite Rapids
+
|successor=Emerald Rapids
−
|successor link=intel/microarchitectures/granite rapids
+
|successor link=intel/microarchitectures/emerald rapids
 
|succession=Yes
 
|succession=Yes
 
}}
 
}}
−
'''Sapphire Rapids''' ('''SPR''') is [[Intel]]'s successor to {{\\|Ice Lake (server)|Ice Lake}}, a [[10 nm]] [[microarchitecture]] for enthusiasts and servers.
+
'''Sapphire Rapids''' ('''SPR''') is [[Intel]]'s successor to {{\\|Ice Lake (server)|Ice Lake}}, a [[7 nm]] [[microarchitecture]] for enthusiasts and servers.
 +
 
 +
== History ==
 +
[[File:intel 2019 investor meeting sapphire roadmap.png|thumb|right|Intel Xeon Roadmap through 2021.]]
 +
Sapphire Rapids was first announced during the May 2019 Intel Investor Meeting. Sapphire Rapids was planned to succeed {{\\|Ice Lake (Server)|Ice Lake}} in 2021, was however delayed to 2023.
  
 
== Process Technology ==
 
== Process Technology ==
−
Sapphire Rapids is planned to be manufactured on Intel's 3rd generation enhanced [[10 nm process|10nm++ process]].
+
Sapphire Rapids is planned to be manufactured on the Intel 7 process (previously 10nm Enhanced SuperFin (ESF)).
 +
 
 +
== Compiler support ==
 +
Support for Sapphire Rapids was added in LLVM Clang 12 and GCC 11.
 +
 
 +
{| class="wikitable"
 +
|-
 +
! Compiler !! Arch-Specific || Arch-Favorable
 +
|-
 +
| [[GCC]] || <code>-march=sapphirerapids</code> || <code>-mtune=sapphirerapids</code>
 +
|-
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| [[LLVM]] || <code>-march=sapphirerapids</code> || <code>-mtune=sapphirerapids</code>
 +
|}
 +
 
 +
=== CPUID ===
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{| class="wikitable tc1 tc2 tc3 tc4"
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 +
|-
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| rowspan="2" | SP || 0 || 0x6 || 0x8 || 0xF
 +
|-
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| colspan="4" | Family 6 Model 143
 +
|}
  
 
== Architecture ==
 
== Architecture ==
−
{{future information}}
 
 
=== Key changes from {{\\|Ice Lake (server)|Ice Lake}}===
 
=== Key changes from {{\\|Ice Lake (server)|Ice Lake}}===
 +
* [[Intel 7]] (from [[10 nm SuperFIN]])
 +
* Core
 +
** {{\\|Sunny Cove}} '''→''' {{\\|Golden Cove}}
 +
* New Integration
 +
** {{intel|Data Streaming Accelerator}} (DSA)
 +
* Memory
 +
** DDR5 (from DDR4)
 +
** Optane DC DIMMs
 +
*** Barlow Pass '''→''' Crow Pass
 +
* I/O
 +
** PCIe Gen 5.0 (from Gen 4.0)
 
* Platform
 
* Platform
−
** {{intel|Whitley|l=platform}} '''→''' {{intel|Tinsley|l=platform}}
+
** {{intel|Whitley|l=platform}} '''→''' {{intel|Eagle Stream|l=platform}}
 +
 
 +
{{expand list}}
 +
 
 +
== See also ==
 +
* {{\\|Golden Cove}}

Latest revision as of 23:26, 12 November 2022

Edit Values
Sapphire Rapids µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2023
ProcessIntel 7
Instructions
ISAx86-64
Succession

Sapphire Rapids (SPR) is Intel's successor to Ice Lake, a 7 nm microarchitecture for enthusiasts and servers.

History[edit]

Intel Xeon Roadmap through 2021.

Sapphire Rapids was first announced during the May 2019 Intel Investor Meeting. Sapphire Rapids was planned to succeed Ice Lake in 2021, was however delayed to 2023.

Process Technology[edit]

Sapphire Rapids is planned to be manufactured on the Intel 7 process (previously 10nm Enhanced SuperFin (ESF)).

Compiler support[edit]

Support for Sapphire Rapids was added in LLVM Clang 12 and GCC 11.

Compiler Arch-Specific Arch-Favorable
GCC -march=sapphirerapids -mtune=sapphirerapids
LLVM -march=sapphirerapids -mtune=sapphirerapids

CPUID[edit]

Core Extended
Family 		Family Extended
Model 		Model
SP 0 0x6 0x8 0xF
Family 6 Model 143

Architecture[edit]

Key changes from Ice Lake[edit]

This list is incomplete; you can help by expanding it.

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/sapphire_rapids&oldid=100926"
Facts about "Sapphire Rapids - Microarchitectures - Intel"
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codenameSapphire Rapids +
designerIntel +
first launched2023 +
full page nameintel/microarchitectures/sapphire rapids +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameSapphire Rapids +