Semiconductor & Computer Engineering
From WikiChip
File list
This special page shows all uploaded files.
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| Date | Name | Thumbnail | Size | User | Description | Versions |
|---|---|---|---|---|---|---|
| 21:40, 25 November 2018 | nec sx-aurora tsubasa package.svg (file) |  |
39 KB | David | NEC {{nec|SX-Aurora|l=arch}} package diagram. | 1 |
| 21:31, 25 November 2018 | sx-aurora chip (annotated).png (file) | .png) |
9.23 MB | David | NEC {{nec|SX-Aurora|l=arch}} package. | 1 |
| 21:19, 25 November 2018 | sx-aurora chip.png (file) |  |
8.48 MB | David | NEC {{nec|SX-Aurora|l=arch}} package. | 1 |
| 10:37, 24 November 2018 | sx-aurora vector core block diagram.svg (file) |  |
185 KB | David | 2 | |
| 22:35, 23 November 2018 | sx-aurora overview.svg (file) |  |
45 KB | David | 2 | |
| 22:33, 23 November 2018 | sx-aurora block diagram.svg (file) |  |
116 KB | David | WikiChip's block diagram of the {{nec|SX-Aurora|l=arch}} chip. | 1 |
| 06:56, 20 November 2018 | NEC logo.svg (file) |  |
2 KB | David | NEC logo. | 1 |
| 17:39, 19 November 2018 | skylake sp xcc block diagram.svg (file) |  |
190 KB | David | WikiChip's block diagram of Intel's {{intel|Skylake|l=arch}} server chip, extreme core count die. | 1 |
| 17:39, 19 November 2018 | skylake sp lcc block diagram.svg (file) |  |
83 KB | David | WikiChip's block diagram of Intel's {{intel|Skylake|l=arch}} server chip, low core count die. | 1 |
| 17:38, 19 November 2018 | skylake sp hcc block diagram.svg (file) |  |
128 KB | David | 2 | |
| 16:35, 19 November 2018 | cascade lake sp 2-way 2 upi.svg (file) |  |
44 KB | David | Intel {{intel|Cascade Lake SP|l=core}} 2-way SMP with 2 {{intel|UPI}} links. WikiChip's own drawing. | 1 |
| 16:34, 19 November 2018 | cascade lake sp 2-way 3 upi.svg (file) |  |
45 KB | David | Intel {{intel|Cascade Lake SP|l=core}} 2-way SMP with 3 {{intel|UPI}} links. WikiChip's own drawing. | 1 |
| 16:34, 19 November 2018 | cascade lake sp 4-way 2 upi.svg (file) |  |
87 KB | David | Intel {{intel|Cascade Lake SP|l=core}} 4-way SMP with 2 {{intel|UPI}} links. WikiChip's own drawing. | 1 |
| 16:34, 19 November 2018 | cascade lake sp 4-way 3 upi.svg (file) |  |
89 KB | David | Intel {{intel|Cascade Lake SP|l=core}} 4-way SMP with 3 {{intel|UPI}} links. WikiChip's own drawing. | 1 |
| 16:33, 19 November 2018 | cascade lake sp 8-way 3 upi.svg (file) |  |
177 KB | David | Intel {{intel|Cascade Lake SP|l=core}} 8-way SMP with 3 {{intel|UPI}} links. WikiChip's own drawing. | 1 |
| 12:49, 19 November 2018 | snia npm dax.png (file) |  |
67 KB | David | SNIA {{snia|NPM}} DAX diagram. | 1 |
| 23:04, 18 November 2018 | amd zen 2 logo.png (file) |  |
31 KB | David | AMD {{amd|Zen 2|l=arch}} logo. | 1 |
| 14:35, 18 November 2018 | next-horizon-zen3-4-roadmap.png (file) |  |
444 KB | David | AMD roadmap including {{amd|Zen 4|l=arch}}. | 1 |
| 11:54, 18 November 2018 | amd naples (back).png (file) | .png) |
11.36 MB | David | AMD {{amd|naples|l=core}}. Image by WikiChip. | 1 |
| 11:53, 18 November 2018 | amd naples (front).png (file) | .png) |
8.06 MB | David | AMD {{amd|naples|l=core}}. Image by WikiChip. | 1 |
| 18:01, 7 November 2018 | float32 encoding format.svg (file) |  |
31 KB | David | float32 encoding format by WikiChip. | 1 |
| 18:01, 7 November 2018 | float16 encoding format.svg (file) |  |
18 KB | David | float16 encoding format by WikiChip. | 1 |
| 18:01, 7 November 2018 | bfloat16 encoding format.svg (file) |  |
18 KB | David | bfloat16 encoding format by WikiChip. | 1 |
| 01:20, 7 November 2018 | vnni-vpdpwssd-i.svg (file) |  |
34 KB | David | x86 {{x86|AVX512 VNNI}} VPDPWSSD. | 1 |
| 01:20, 7 November 2018 | vnni-vpdpbusd-i.svg (file) |  |
34 KB | David | x86 {{x86|AVX512 VNNI}} VPDPBUSD. | 1 |
| 01:07, 7 November 2018 | vnni-vpdpbusd.svg (file) |  |
78 KB | David | x86 {{x86|AVX512 VNNI}} VPDPBUSD. | 1 |
| 01:03, 7 November 2018 | vnni-vpdpwssd.svg (file) |  |
70 KB | David | x86 {{x86|AVX512 VNNI}} VPDPWSSD. | 1 |
| 23:27, 4 November 2018 | sifive 7 series cores with fio port.svg (file) |  |
35 KB | David | SiFive {{sifive|7 Series|l=arch}} With FIO Ports. | 1 |
| 23:24, 4 November 2018 | sifive 7 series core with fio port.svg (file) |  |
14 KB | David | SiFive {{sifive|7 Series|l=arch}} Fast I/O Port. | 1 |
| 23:10, 4 November 2018 | 7 series pipeline.svg (file) |  |
16 KB | David | SiFive {{sifive|7 Series|l=arch}} pipeline. | 1 |
| 21:30, 4 November 2018 | sifive 7 series block diagram.svg (file) |  |
38 KB | David | SiFive {{sifive|7 Series|l=arch}} block diagram. | 1 |
| 21:29, 4 November 2018 | sifive 7 series cluster.svg (file) |  |
25 KB | David | SiFive {{sifive|7 Series|l=arch}} cluster. | 1 |
| 13:36, 2 November 2018 | A12X.png (file) |  |
269 KB | Bonusround | 1 | |
| 10:52, 24 October 2018 | kx-6000 (front).png (file) | .png) |
145 KB | David | zhaoxin {{zhaoxin|kaixian}} | 1 |
| 01:34, 24 October 2018 | coffee lake ring addition.png (file) |  |
1.74 MB | David | Intel {{intel|Coffee Lake|l=arch}} ring addition. Image by WikiChip. | 1 |
| 01:30, 24 October 2018 | coffee lake ring explanation 1.svg (file) |  |
36 KB | David | Intel {{intel|Coffee Lake|l=arch}} ring. | 1 |
| 01:26, 24 October 2018 | coffee lake r wafer.png (file) |  |
24.75 MB | David | Intel {{intel|Coffee Lake|Coffee Lake R|l=arch}} wafer. Image by Intel. | 1 |
| 01:20, 24 October 2018 | coffee lake die (octa core) (annotated).png (file) | _(annotated).png) |
2.91 MB | David | Intel {{intel|Coffee Lake|l=arch|Coffee Lake Refresh}} die shot. Image by Intel. Annotated by WikiChip. * Original: File:coffee_lake_die_(octa_core).png | 1 |
| 01:20, 24 October 2018 | coffee lake die (octa core).png (file) | .png) |
3.23 MB | David | Intel {{intel|Coffee Lake|l=arch|Coffee Lake Refresh}} die shot. Image by Intel. * Annotated: coffee_lake_die_(octa_core)_(annotated).png | 1 |
| 01:08, 24 October 2018 | 9th-gen-core-desktop-brief.pdf (file) |  |
19.33 MB | David | 9th gen core desktop PB. | 1 |
| 14:20, 23 October 2018 | sdm675-brief.pdf (file) |  |
664 KB | David | Qualcomm Snapdragon 675 PB. | 1 |
| 01:22, 15 October 2018 | coffee lake-coffee lake refresh overview change.svg (file) |  |
43 KB | David | General system architecture change from {{intel|Coffee Lake|l=arch}} to Coffee Lake Refresh. | 1 |
| 00:51, 15 October 2018 | coffee lake r soc block diagram.svg (file) |  |
40 KB | David | My drawing of {{intel|Coffee Lake|l=arch}} R SOC in a block diagram. | 1 |
| 11:09, 9 October 2018 | Intel-9th-Gen-Core-1.jpg (file) |  |
15.74 MB | David | Core i9-9900K view. Image by Intel. | 1 |
| 11:05, 9 October 2018 | core i9-9900k (front).png (file) | .png) |
9.96 MB | David | Core i9-9900K, front. Image by Intel. | 1 |
| 16:56, 7 October 2018 | power9 su die (annotated).png (file) | .png) |
3.64 MB | David | 4 | |
| 11:49, 5 October 2018 | gti logo.jpeg (file) |  |
7 KB | David | [[Gyrfalcon Technology] logo. | 1 |
| 11:52, 4 October 2018 | cnp ds listing.png (file) |  |
44 KB | At32Hz | {{intel|Cannon Point|l=chipset}} | 1 |
| 13:15, 2 October 2018 | csa with memory subsys.svg (file) |  |
22 KB | David | 2 | |
| 23:53, 1 October 2018 | csa switch network.svg (file) |  |
45 KB | David | Intel {{intel|CSA}} switch network. Image by WikiChip. | 1 |
_(annotated).png&action=edit&redlink=1){kind=link}
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