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Information for "sifive/microarchitectures/7 series"
Basic information
| Display title | 7 Series - Microarchitectures - SiFive |
| Default sort key | 7 Series, SiFive |
| Page length (in bytes) | 4,270 |
| Page ID | 31767 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 19:56, 4 November 2018 |
| Latest editor | 46.109.192.167 (talk) |
| Date of latest edit | 08:16, 28 November 2018 |
| Total number of edits | 8 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (10) | Templates used on this page:
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Facts about "7 Series - Microarchitectures - SiFive"
| codename | 7 Series + |
| core count | 1 +, 2 +, 4 +, 6 + and 8 + |
| designer | SiFive + |
| first launched | October 21, 2018 + |
| full page name | sifive/microarchitectures/7 series + |
| instance of | microarchitecture + |
| instruction set architecture | RISC-V + |
| manufacturer | TSMC + and GlobalFoundries + |
| microarchitecture type | CPU + |
| name | 7 Series + |
| pipeline stages | 8 + |