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Information for "movidius/microarchitectures/shave v2.0"
Basic information
Display title | SHAVE v2.0 - Microarchitectures - Intel Movidius |
Default sort key | SHAVE v2.0, Movidius |
Page length (in bytes) | 12,252 |
Page ID | 28577 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 1 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | Inject (talk | contribs) |
Date of page creation | 08:02, 10 March 2018 |
Latest editor | 49.178.54.248 (talk) |
Date of latest edit | 18:05, 20 January 2021 |
Total number of edits | 39 |
Total number of distinct authors | 5 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
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Facts about "SHAVE v2.0 - Microarchitectures - Intel Movidius"
codename | SHAVE v2.0 + |
designer | Movidius + |
first launched | 2011 + |
full page name | movidius/microarchitectures/shave v2.0 + |
instance of | microarchitecture + |
instruction set architecture | SHAVE + and SPARC v8 + |
manufacturer | TSMC + |
name | SHAVE v2.0 + |
phase-out | 2014 + |
process | 65 nm (0.065 μm, 6.5e-5 mm) + |