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Information for "intel/xeon silver/4210r"
Basic information
| Display title | Xeon Silver 4210R - Intel |
| Default sort key | Xeon Silver 4210R, Intel |
| Page length (in bytes) | 4,370 |
| Page ID | 35944 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 09:11, 28 February 2020 |
| Latest editor | 99.82.163.45 (talk) |
| Date of latest edit | 10:21, 4 May 2020 |
| Total number of edits | 5 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (22) | Templates used on this page:
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Facts about "Xeon Silver 4210R - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Silver 4210R - Intel#pcie + |
| base frequency | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
| bus links | 4 + |
| bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
| bus type | DMI 3.0 + |
| chipset | Lewisburg + |
| clock multiplier | 24 + |
| core count | 10 + |
| core family | 6 + |
| core name | Cascade Lake R + |
| designer | Intel + |
| family | Xeon Silver + |
| first announced | February 24, 2020 + |
| first launched | February 24, 2020 + |
| full page name | intel/xeon silver/4210r + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has advanced vector extensions 512 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
| has intel deep learning boost | true + |
| has intel enhanced speedstep technology | true + |
| has intel speed shift technology | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) + |
| ldate | February 24, 2020 + |
| main image | |
| manufacturer | Intel + |
| market segment | Server + |
| max case temperature | 357.15 K (84 °C, 183.2 °F, 642.87 °R) + |
| max cpu count | 2 + |
| max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
| max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
| max memory channels | 6 + |
| microarchitecture | Cascade Lake + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| model number | 4210R + |
| name | Xeon Silver 4210R + |
| package | FCLGA-3647 + |
| platform | Purley + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| release price | $ 511.00 (€ 459.90, £ 413.91, ¥ 52,801.63) + and $ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) + |
| release price (box) | $ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) + |
| release price (tray) | $ 511.00 (€ 459.90, £ 413.91, ¥ 52,801.63) + |
| series | 4200 + |
| smp interconnect | UPI + |
| smp interconnect links | 2 + |
| smp interconnect rate | 9.6 GT/s + |
| smp max ways | 2 + |
| socket | Socket P + and LGA-3647 + |
| supported memory type | DDR4-2400 + |
| tdp | 100 W (100,000 mW, 0.134 hp, 0.1 kW) + |
| technology | CMOS + |
| thread count | 20 + |
| turbo frequency (1 core) | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |