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Information for "intel/microarchitectures/p5"
Basic information
Display title | P5 - Microarchitectures - Intel |
Default sort key | P5, Intel |
Page length (in bytes) | 842 |
Page ID | 6777 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 6 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | At32Hz (talk | contribs) |
Date of page creation | 22:37, 14 April 2016 |
Latest editor | Mys 721tx (talk | contribs) |
Date of latest edit | 18:34, 30 November 2017 |
Total number of edits | 11 |
Total number of distinct authors | 4 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (8) | Templates used on this page:
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Facts about "P5 - Microarchitectures - Intel"
codename | P5 + |
designer | Intel + |
first launched | April 1993 + |
full page name | intel/microarchitectures/p5 + |
instance of | microarchitecture + |
instruction set architecture | x86-32 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | P5 + |
phase-out | October 1995 + |
process | 600 nm (0.6 μm, 6.0e-4 mm) + |