From WikiChip
Information for "intel/microarchitectures/lakefield"

Basic information

Display titleLakefield - Microarchitectures - Intel
Default sort keyLakefield, Intel
Page length (in bytes)5,414
Page ID34417
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page1
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

Page protection

EditAllow all users (infinite)
MoveAllow all users (infinite)

Edit history

Page creatorDavid (talk | contribs)
Date of page creation09:19, 10 May 2019
Latest editor211.22.182.201 (talk)
Date of latest edit05:44, 14 August 2021
Total number of edits9
Total number of distinct authors2
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

Page properties

Hidden category (1)

This page is a member of 1 hidden category:

Transcluded templates (14)

Templates used on this page:

codenameLakefield +
core count5 +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/lakefield +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameLakefield +
process22 nm (0.022 μm, 2.2e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) +