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Information for "intel/microarchitectures/alder lake"
Basic information
Display title | Alder Lake - Microarchitectures - Intel |
Default sort key | Alder Lake, Intel |
Page length (in bytes) | 7,705 |
Page ID | 29183 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 6 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | ChipIt (talk | contribs) |
Date of page creation | 23:41, 5 April 2018 |
Latest editor | 95.24.51.101 (talk) |
Date of latest edit | 22:07, 5 March 2025 |
Total number of edits | 69 |
Total number of distinct authors | 33 |
Recent number of edits (within past 90 days) | 1 |
Recent number of distinct authors | 1 |
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Facts about "Alder Lake - Microarchitectures - Intel"
codename | Alder Lake + |
core count | 16 +, 14 +, 10 + and 6 + |
designer | Intel + |
first launched | 2021 + |
full page name | intel/microarchitectures/alder lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Alder Lake + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |
processing element count | 8P/8E +, 6P/8E +, 2P/8E +, 6P/0E +, 32 EU iGPU + and 96 EU iGPU + |