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Information for "intel/cores/skyhawk lake"
Basic information
Display title | Skyhawk Lake - Cores - Intel |
Default sort key | Skyhawk Lake, Intel |
Page length (in bytes) | 954 |
Page ID | 34782 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 0 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 12:17, 4 June 2019 |
Latest editor | 99.82.163.46 (talk) |
Date of latest edit | 02:57, 7 May 2020 |
Total number of edits | 3 |
Total number of distinct authors | 3 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
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Facts about "Skyhawk Lake - Cores - Intel"
designer | Intel + |
first announced | 2020 + |
first launched | 2020 + |
instance of | core + |
isa | x86-64 + |
manufacturer | Intel + |
microarchitecture | Tremont + |
name | Skyhawk Lake + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |