Information for "intel/celeron/n3050"

Basic information

Display title	Celeron N3050 - Intel
Default sort key	Celeron N3050, Intel
Page length (in bytes)	4,515
Page ID	6643
Page content language	English (en)
Page content model	wikitext
Indexing by robots	Allowed
Number of redirects to this page	12
Counted as a content page	Yes
Number of subpages of this page	0 (0 redirects; 0 non-redirects)

Edit	Allow all users (infinite)
Move	Allow all users (infinite)

Page creator	At32Hz (talk \| contribs)
Date of page creation	21:50, 10 April 2016
Latest editor	24.186.250.71 (talk)
Date of latest edit	08:40, 8 July 2022
Total number of edits	20
Total number of distinct authors	9
Recent number of edits (within past 90 days)	0
Recent number of distinct authors	0

Transcluded templates (20)	Templates used on this page: Template:!- (edit) Template:arch (view source) (protected) Template:cache info (view source) (protected) Template:chip (view source) (protected) Template:comma (edit) Template:expand list (edit) Template:expansions (edit) Template:integrated graphic (edit) Template:integrated memory controller (edit) Template:intel (view source) (protected) Template:intel title (view source) (protected) Template:istrue (view source) (protected) Template:link-intel (view source) (protected) Template:link-x86 (view source) (protected) Template:main (view source) (protected) Template:url parse anchor (view source) (protected) Template:url parse article (view source) (protected) Template:x86 (view source) (protected) Template:x86 features (view source) (protected) Module:chip (view source)

has feature	integrated gpu +
integrated gpu	HD Graphics (Braswell) +
integrated gpu base frequency	320 MHz (0.32 GHz, 320,000 KHz) +
integrated gpu max frequency	600 MHz (0.6 GHz, 600,000 KHz) +
l1d$ description	6-way set associative +
l1i$ description	8-way set associative +
l2$ description	16-way set associative +
l3$ description	No L3$ +
l3$ size	0 MiB (0 KiB, 0 B, 0 GiB) +