Information for "cavium/octeon plus/cn5850-600bg1521-nsp"

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Display title	CN5850-600 NSP - Cavium
Default sort key	CN5850-600 NSP, Cavium
Page length (in bytes)	3,813
Page ID	12270
Page content language	English (en)
Page content model	wikitext
Indexing by robots	Allowed
Number of redirects to this page	6
Counted as a content page	Yes
Number of subpages of this page	0 (0 redirects; 0 non-redirects)

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Page creator	ChipIt (talk \| contribs)
Date of page creation	23:08, 14 December 2016
Latest editor	ChippyBot (talk \| contribs)
Date of latest edit	15:12, 13 December 2017
Total number of edits	10
Total number of distinct authors	2
Recent number of edits (within past 90 days)	0
Recent number of distinct authors	0

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Transcluded templates (16)	Templates used on this page: Template:accelerators (edit) Template:arch (view source) (protected) Template:cache size (view source) (protected) Template:cavium (edit) Template:cavium title (edit) Template:chip (view source) (protected) Template:expansions (edit) Template:istrue (view source) (protected) Template:link-cavium (edit) Template:main (view source) (protected) Template:memory controller (edit) Template:network (edit) Template:packages/cavium/fcbga-1521 (edit) Template:url parse anchor (view source) (protected) Template:url parse article (view source) (protected) Module:chip (view source)

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN5850-600 NSP - Cavium#package +
base frequency	600 MHz (0.6 GHz, 600,000 kHz) +
core count	12 +
designer	Cavium +
family	OCTEON Plus +
first announced	October 9, 2006 +
first launched	February 2007 +
full page name	cavium/octeon plus/cn5850-600bg1521-nsp +
has ecc memory support	true +
has hardware accelerators for cryptography	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for regular expression	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	576 KiB (589,824 B, 0.563 MiB) +
l1d$ description	64-way set associative +
l1d$ size	192 KiB (196,608 B, 0.188 MiB) +
l1i$ description	64-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	8-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	February 2007 +
main image	+
manufacturer	TSMC +
market segment	Network +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN5850-600 NSP +
name	Cavium CN5850-600 NSP +
package	FCBGA-1521 +
part number	CN5850-600BG1521-NSP +
process	90 nm (0.09 μm, 9.0e-5 mm) +
series	CN58xx +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	12 +
word size	64 bit (8 octets, 16 nibbles) +

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