Information for "cavium/octeon plus/cn5740-600bg1217-ssp"

Basic information

Display title	CN5740-600 SSP - Cavium
Default sort key	CN5740-600 SSP, Cavium
Page length (in bytes)	3,797
Page ID	12367
Page content language	English (en)
Page content model	wikitext
Indexing by robots	Allowed
Number of redirects to this page	6
Counted as a content page	Yes
Number of subpages of this page	0 (0 redirects; 0 non-redirects)

Page protection

Edit	Allow all users (infinite)
Move	Allow all users (infinite)

Edit history

Page creator	ChipIt (talk \| contribs)
Date of page creation	21:42, 28 December 2016
Latest editor	ChippyBot (talk \| contribs)
Date of latest edit	16:12, 13 December 2017
Total number of edits	6
Total number of distinct authors	2
Recent number of edits (within past 90 days)	0
Recent number of distinct authors	0

Page properties

Transcluded templates (18)	Templates used on this page: Template:accelerators (edit) Template:arch (view source) (protected) Template:cache size (view source) (protected) Template:cavium (edit) Template:cavium title (edit) Template:chip (view source) (protected) Template:expansions (edit) Template:istrue (view source) (protected) Template:link-cavium (edit) Template:link-packages (edit) Template:main (view source) (protected) Template:memory controller (edit) Template:network (edit) Template:packages (edit) Template:packages/cavium/fcbga-1217 (edit) Template:url parse anchor (view source) (protected) Template:url parse article (view source) (protected) Module:chip (view source)

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN5740-600 SSP - Cavium#package + and CN5740-600 SSP - Cavium#io +
base frequency	600 MHz (0.6 GHz, 600,000 kHz) +
core count	8 +
designer	Cavium +
family	OCTEON Plus +
first announced	June 26, 2007 +
first launched	August 2007 +
full page name	cavium/octeon plus/cn5740-600bg1217-ssp +
has ecc memory support	true +
has hardware accelerators for cryptography	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
has hardware raid 5 support	true +
has hardware raid 6 support	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	384 KiB (393,216 B, 0.375 MiB) +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	August 2007 +
main image	+
manufacturer	TSMC +
market segment	Storage +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	2 +
max pcie lanes	8 +
microarchitecture	cnMIPS +
model number	CN5740-600 SSP +
name	Cavium CN5740-600 SSP +
package	FCBGA-1217 +
part number	CN5740-600BG1217-SSP +
process	90 nm (0.09 μm, 9.0e-5 mm) +
series	CN57xx +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	8 +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung

Basic information

Page protection

Edit history

Page properties