From WikiChip
Information for "cavium/octeon plus/cn5734-900bg1217-sp"
Basic information
Display title | CN5734-900 SP - Cavium |
Default sort key | CN5734-900 SP, Cavium |
Page length (in bytes) | 3,655 |
Page ID | 12371 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 6 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | ChipIt (talk | contribs) |
Date of page creation | 21:42, 28 December 2016 |
Latest editor | ChippyBot (talk | contribs) |
Date of latest edit | 16:12, 13 December 2017 |
Total number of edits | 6 |
Total number of distinct authors | 2 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (18) | Templates used on this page:
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Facts about "CN5734-900 SP - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5734-900 SP - Cavium#io + |
has ecc memory support | true + |
has hardware accelerators for data compression | true + |
has hardware accelerators for data decompression | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
has hardware raid 5 support | true + |
has hardware raid 6 support | true + |
l1$ size | 288 KiB (294,912 B, 0.281 MiB) + |
l1d$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 8 + |
supported memory type | DDR2-800 + |