Semiconductor & Computer Engineering
From WikiChip
Information for "cavium/octeon/cn3860-500bg1521-scp"
Basic information
| Display title | CN3860-500 SCP - Cavium |
| Default sort key | CN3860-500 SCP, Cavium |
| Page length (in bytes) | 3,793 |
| Page ID | 12148 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 6 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | ChipIt (talk | contribs) |
| Date of page creation | 18:16, 10 December 2016 |
| Latest editor | ChippyBot (talk | contribs) |
| Date of latest edit | 15:11, 13 December 2017 |
| Total number of edits | 7 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (16) | Templates used on this page:
|
Facts about "CN3860-500 SCP - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN3860-500 SCP - Cavium#package + |
| base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + |
| core count | 16 + |
| core name | cnMIPS + |
| designer | Cavium + |
| family | OCTEON + |
| first announced | September 13, 2004 + |
| first launched | June 1, 2005 + |
| full page name | cavium/octeon/cn3860-500bg1521-scp + |
| has ecc memory support | true + |
| has hardware accelerators for cryptography | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| instance of | microprocessor + |
| isa | MIPS64 + |
| isa family | MIPS + |
| l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 64-way set associative + |
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| ldate | June 1, 2005 + |
| main image |  + |
| manufacturer | TSMC + |
| market segment | Networking + |
| max cpu count | 1 + |
| max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 1 + |
| microarchitecture | cnMIPS + |
| model number | CN3860-500 SCP + |
| name | Cavium CN3860-500 SCP + |
| package | FCBGA-1521 + |
| part number | CN3860-500BG1521-SCP + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| series | CN3800 + |
| smp max ways | 1 + |
| supported memory type | DDR2-800 + |
| technology | CMOS + |
| thread count | 16 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
