From WikiChip
Information for "cavium/octeon/cn3840-500bg1521-nsp"

Basic information

Display titleCN3840-500 NSP - Cavium
Default sort keyCN3840-500 NSP, Cavium
Page length (in bytes)3,849
Page ID12124
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page6
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

Page protection

EditAllow all users (infinite)
MoveAllow all users (infinite)

Edit history

Page creatorChipIt (talk | contribs)
Date of page creation19:16, 10 December 2016
Latest editorChippyBot (talk | contribs)
Date of latest edit16:11, 13 December 2017
Total number of edits7
Total number of distinct authors2
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

Page properties

Transcluded templates (16)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/cavium/octeon/cn3840-500bg1521-nsp"
Facts about "CN3840-500 NSP - Cavium"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN3840-500 NSP - Cavium#package +
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count8 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedSeptember 13, 2004 +
first launchedJune 1, 2005 +
full page namecavium/octeon/cn3840-500bg1521-nsp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size320 KiB (327,680 B, 0.313 MiB) +
l1d$ description64-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description64-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateJune 1, 2005 +
main imageFile:octeon cn38xx.png +
manufacturerTSMC +
market segmentNetworking +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3840-500 NSP +
nameCavium CN3840-500 NSP +
packageFCBGA-1521 +
part numberCN3840-500BG1521-NSP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3800 +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +