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Information for "cavium/octeon/cn3120-550bg868-nsp"

Basic information

Display titleCN3120-550 NSP - Cavium
Default sort keyCN3120-550 NSP, Cavium
Page length (in bytes)4,148
Page ID12037
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page6
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

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Edit history

Page creatorChipIt (talk | contribs)
Date of page creation00:00, 9 December 2016
Latest editorChippyBot (talk | contribs)
Date of latest edit16:11, 13 December 2017
Total number of edits15
Total number of distinct authors2
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

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Transcluded templates (16)

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has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
l1$ size80 KiB (81,920 B, 0.0781 MiB) +
l1d$ description64-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
max memory bandwidth4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels1 +
supported memory typeDDR2-667 +