Semiconductor & Computer Engineering
From WikiChip
Information for "cavium/octeon/cn3120-500bg868-cp"
Basic information
| Display title | CN3120-500 CP - Cavium |
| Default sort key | CN3120-500 CP, Cavium |
| Page length (in bytes) | 3,936 |
| Page ID | 12048 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 6 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | ChipIt (talk | contribs) |
| Date of page creation | 00:06, 9 December 2016 |
| Latest editor | ChippyBot (talk | contribs) |
| Date of latest edit | 16:11, 13 December 2017 |
| Total number of edits | 12 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (16) | Templates used on this page:
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Facts about "CN3120-500 CP - Cavium"
| has ecc memory support | true + |
| l1$ size | 80 KiB (81,920 B, 0.0781 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
| max memory bandwidth | 4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) + |
| max memory channels | 1 + |
| supported memory type | DDR2-667 + |