Semiconductor & Computer Engineering
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Information for "cavium/microarchitectures/cnmips"
Basic information
| Display title | cnMIPS - Microarchitectures - Cavium |
| Default sort key | cnMIPS, Cavium |
| Page length (in bytes) | 6,686 |
| Page ID | 11963 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 1 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | ChipIt (talk | contribs) |
| Date of page creation | 22:11, 6 December 2016 |
| Latest editor | ChippyBot (talk | contribs) |
| Date of latest edit | 19:38, 23 June 2017 |
| Total number of edits | 23 |
| Total number of distinct authors | 3 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (14) | Templates used on this page:
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Facts about "cnMIPS - Microarchitectures - Cavium"
| codename | cnMIPS + |
| core count | 2 + and 4 + |
| designer | Cavium + |
| first launched | September 13, 2004 + |
| full page name | cavium/microarchitectures/cnmips + |
| instance of | microarchitecture + |
| instruction set architecture | MIPS64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | cnMIPS + |
| pipeline stages | 5 + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |