Semiconductor & Computer Engineering
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Information for "arm holdings/microarchitectures/cortex-a75"
Basic information
| Display title | Cortex-A75 - Microarchitectures - ARM |
| Default sort key | Cortex-A75, ARM Holdings |
| Page length (in bytes) | 2,100 |
| Page ID | 18228 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 17 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | ChipIt (talk | contribs) |
| Date of page creation | 08:03, 29 May 2017 |
| Latest editor | 88.242.68.86 (talk) |
| Date of latest edit | 02:26, 6 May 2024 |
| Total number of edits | 20 |
| Total number of distinct authors | 5 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (12) | Templates used on this page:
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Facts about "Cortex-A75 - Microarchitectures - ARM"
| codename | Cortex-A75 + |
| core count | 1 + and 2 + |
| designer | ARM Holdings + |
| first launched | May 29, 2017 + |
| full page name | arm holdings/microarchitectures/cortex-a75 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.2 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A75 + |
| pipeline stages (max) | 13 + |
| pipeline stages (min) | 11 + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |