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Information for "arm holdings/microarchitectures/cortex-a55"
Basic information
| Display title | Cortex-A55 - Microarchitectures - ARM |
| Default sort key | Cortex-A55, ARM Holdings |
| Page length (in bytes) | 4,458 |
| Page ID | 18226 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 20 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | ChipIt (talk | contribs) |
| Date of page creation | 07:34, 29 May 2017 |
| Latest editor | 156.194.123.3 (talk) |
| Date of latest edit | 04:23, 27 April 2023 |
| Total number of edits | 30 |
| Total number of distinct authors | 13 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
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| Transcluded templates (18) | Templates used on this page:
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Facts about "Cortex-A55 - Microarchitectures - ARM"
| codename | Cortex-A55 + |
| core count | 1 +, 2 +, 3 + and 4 + |
| designer | ARM Holdings + |
| first launched | May 29, 2017 + |
| full page name | arm holdings/microarchitectures/cortex-a55 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.2 + |
| manufacturer | TSMC +, Samsung +, GlobalFoundries + and SMIC + |
| microarchitecture type | CPU + |
| name | Cortex-A55 + |
| pipeline stages | 8 + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) + |