Information for "amd/epyc"

Basic information

Display title	EPYC - AMD
Default sort key	EPYC, AMD
Page length (in bytes)	19,573
Page ID	18123
Page content language	English (en)
Page content model	wikitext
Indexing by robots	Allowed
Number of redirects to this page	4
Counted as a content page	Yes
Number of subpages of this page	76 (0 redirects; 76 non-redirects)

Edit	Allow all users (infinite)
Move	Allow all users (infinite)

Page creator	Inject (talk \| contribs)
Date of page creation	17:38, 16 May 2017
Latest editor	71.183.100.89 (talk)
Date of latest edit	06:21, 22 May 2024
Total number of edits	37
Total number of distinct authors	11
Recent number of edits (within past 90 days)	0
Recent number of distinct authors	0

Transcluded templates (24)	Templates used on this page: Template:!- (edit) Template:amd (edit) Template:amd title (view source) (protected) Template:arch (view source) (protected) Template:cavium (edit) Template:chip identification (edit) Template:collist (edit) Template:comma2 (edit) Template:comp table count (edit) Template:comp table end (edit) Template:comp table start (edit) Template:ic family (edit) Template:intel (view source) (protected) Template:link-amd (edit) Template:link-cavium (edit) Template:link-intel (view source) (protected) Template:link-qualcomm (edit) Template:link-x86 (view source) (protected) Template:proc table 3 (view source) (protected) Template:qualcomm (edit) Template:see also (edit) Template:url parse anchor (view source) (protected) Template:url parse article (view source) (protected) Template:x86 (view source) (protected)

designer	AMD +
first announced	May 16, 2017 +
first launched	June 20, 2017 +
full page name	amd/epyc +
instance of	system on a chip family +
instruction set architecture	x86-64 +
main designer	AMD +
manufacturer	GlobalFoundries + and TSMC +
microarchitecture	Zen +, Zen 2 +, Zen 3 + and Zen 4 +
name	AMD EPYC +
package	FCLGA-4094 + and FCLGA-? +
process	14 nm (0.014 μm, 1.4e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) +
socket	Socket SP3 + and Socket SP5 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +