Semiconductor & Computer Engineering
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Information for "alchemy/microarchitectures/au1"
Basic information
| Display title | Au1 - Microarchitectures - Alchemy |
| Default sort key | Au1, Alchemy |
| Page length (in bytes) | 13,626 |
| Page ID | 36620 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 3 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | QuietRub (talk | contribs) |
| Date of page creation | 01:13, 20 March 2022 |
| Latest editor | QuietRub (talk | contribs) |
| Date of latest edit | 15:00, 17 April 2022 |
| Total number of edits | 2 |
| Total number of distinct authors | 1 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (10) | Templates used on this page:
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Facts about "Au1 - Microarchitectures - Alchemy"
| codename | Au1 + |
| core count | 1 + |
| designer | Alchemy + |
| first launched | June 13, 2000 + |
| full page name | alchemy/microarchitectures/au1 + |
| instance of | microarchitecture + |
| instruction set architecture | MIPS32 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Au1 + |
| pipeline stages | 5 + |
| process | 180 nm (0.18 μm, 1.8e-4 mm) + and 130 nm (0.13 μm, 1.3e-4 mm) + |