Revision history of "cmu/piperench"

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base frequency	120 MHz (0.12 GHz, 120,000 kHz) +
bus speed	60 MHz (0.06 GHz, 60,000 kHz) +
clock multiplier	2 +
designer	Carnegie Mellon University +
die area	49 mm² (0.076 in², 0.49 cm², 49,000,000 µm²) +
first announced	April 2000 +
first launched	2002 +
full page name	cmu/piperench +
instance of	microprocessor +
ldate	2002 +
main image	+
main image caption	Logo +
name	PipeRench +
power dissipation	4 W (4,000 mW, 0.00536 hp, 0.004 kW) +
process	180 nm (0.18 μm, 1.8e-4 mm) +
technology	CMOS +
transistor count	3,650,000 +

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