Revision history of "cavium/octeon plus/cn5860-800bg1521-nsp"

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(cur | prev) 16:13, 13 December 2017‎ ChippyBot (talk | contribs)‎ m . . (3,816 bytes) (+1)‎ . . (Bot: moving all {{mpu}} to {{chip}}) (undo)
(cur | prev) 18:16, 30 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,815 bytes) (0)‎ . . (Bot: corrected param) (undo)
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(cur | prev) 19:31, 27 December 2016‎ ChipIt (talk | contribs)‎ . . (4,049 bytes) (-1)‎ . . (undo)
(cur | prev) 00:06, 16 December 2016‎ ChipIt (talk | contribs)‎ . . (4,050 bytes) (+160)‎ . . (undo)
(cur | prev) 23:37, 15 December 2016‎ ChipIt (talk | contribs)‎ . . (3,890 bytes) (+749)‎ . . (undo)
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(cur | prev) 00:26, 15 December 2016‎ ChipIt (talk | contribs)‎ . . (2,350 bytes) (+2)‎ . . (undo)
(cur | prev) 00:09, 15 December 2016‎ ChipIt (talk | contribs)‎ . . (2,348 bytes) (+2,348)‎ . . (Created page with "{{cavium title|CN5860-800 NSP}} {{mpu | name = Cavium CN5860-800 NSP | no image = | image = octeon plus chip.png | image size...")

has ecc memory support	true +
has hardware accelerators for cryptography	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for regular expression	true +
has hardware accelerators for tcp packet processing	true +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	64-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	64-way set associative +
l1i$ size	512 KiB (524,288 B, 0.5 MiB) +
l2$ description	8-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	1 +
supported memory type	DDR2-800 +

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