Revision history of "cavium/octeon plus/cn5840-900bg1521-scp"

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(cur | prev) 15:12, 13 December 2017‎ ChippyBot (talk | contribs)‎ m . . (3,734 bytes) (+1)‎ . . (Bot: moving all {{mpu}} to {{chip}}) (undo)
(cur | prev) 17:12, 30 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,733 bytes) (0)‎ . . (Bot: corrected param) (undo)
(cur | prev) 21:49, 22 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,733 bytes) (-234)‎ . . (Bot: change package to new layout) (undo)
(cur | prev) 18:30, 27 December 2016‎ ChipIt (talk | contribs)‎ . . (3,967 bytes) (-1)‎ . . (undo)
(cur | prev) 23:04, 15 December 2016‎ ChipIt (talk | contribs)‎ . . (3,968 bytes) (+160)‎ . . (undo)
(cur | prev) 22:45, 15 December 2016‎ ChipIt (talk | contribs)‎ . . (3,808 bytes) (+671)‎ . . (undo)
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(cur | prev) 23:25, 14 December 2016‎ ChipIt (talk | contribs)‎ . . (2,348 bytes) (+2)‎ . . (undo)
(cur | prev) 23:08, 14 December 2016‎ ChipIt (talk | contribs)‎ . . (2,346 bytes) (+2,346)‎ . . (Created page with "{{cavium title|CN5840-900 SCP}} {{mpu | name = Cavium CN5840-900 SCP | no image = | image = octeon plus chip.png | image size...")

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN5840-900 SCP - Cavium#package +
base frequency	900 MHz (0.9 GHz, 900,000 kHz) +
core count	8 +
designer	Cavium +
family	OCTEON Plus +
first announced	October 9, 2006 +
first launched	February 2007 +
full page name	cavium/octeon plus/cn5840-900bg1521-scp +
has ecc memory support	true +
has hardware accelerators for cryptography	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	384 KiB (393,216 B, 0.375 MiB) +
l1d$ description	64-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	64-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	8-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	February 2007 +
main image	+
manufacturer	TSMC +
market segment	Network +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN5840-900 SCP +
name	Cavium CN5840-900 SCP +
package	FCBGA-1521 +
part number	CN5840-900BG1521-SCP +
process	90 nm (0.09 μm, 9.0e-5 mm) +
series	CN58xx +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	8 +
word size	64 bit (8 octets, 16 nibbles) +

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