Revision history of "cavium/octeon plus/cn5734-900bg1217-sp"

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(cur | prev) 15:12, 13 December 2017‎ ChippyBot (talk | contribs)‎ m . . (3,655 bytes) (+1)‎ . . (Bot: moving all {{mpu}} to {{chip}}) (undo)
(cur | prev) 17:04, 30 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,654 bytes) (0)‎ . . (Bot: corrected param) (undo)
(cur | prev) 23:24, 22 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,654 bytes) (-244)‎ . . (Bot: change package to new layout) (undo)
(cur | prev) 13:29, 29 December 2016‎ ChipIt (talk | contribs)‎ . . (3,898 bytes) (+1,090)‎ . . (undo)
(cur | prev) 23:52, 28 December 2016‎ ChipIt (talk | contribs)‎ . . (2,808 bytes) (+473)‎ . . (undo)
(cur | prev) 20:42, 28 December 2016‎ ChipIt (talk | contribs)‎ . . (2,335 bytes) (+2,335)‎ . . (Created page with "{{cavium title|CN5734-900 SP}} {{mpu | name = Cavium CN5734-900 SP | no image = | image = Octeon CN57xx.svg | image size = |...")

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN5734-900 SP - Cavium#package + and CN5734-900 SP - Cavium#io +
base frequency	900 MHz (0.9 GHz, 900,000 kHz) +
core count	6 +
designer	Cavium +
family	OCTEON Plus +
first announced	June 26, 2007 +
first launched	August 2007 +
full page name	cavium/octeon plus/cn5734-900bg1217-sp +
has ecc memory support	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
has hardware raid 5 support	true +
has hardware raid 6 support	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	288 KiB (294,912 B, 0.281 MiB) +
l1d$ size	96 KiB (98,304 B, 0.0938 MiB) +
l1i$ size	192 KiB (196,608 B, 0.188 MiB) +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	August 2007 +
main image	+
manufacturer	TSMC +
market segment	Storage +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	2 +
max pcie lanes	8 +
microarchitecture	cnMIPS +
model number	CN5734-900 SP +
name	Cavium CN5734-900 SP +
package	FCBGA-1217 +
part number	CN5734-900BG1217-SP +
process	90 nm (0.09 μm, 9.0e-5 mm) +
series	CN57xx +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	6 +
word size	64 bit (8 octets, 16 nibbles) +

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