Revision history of "cavium/octeon/cn3860-500bg1521-exp"

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(cur | prev) 15:11, 13 December 2017‎ ChippyBot (talk | contribs)‎ m . . (3,741 bytes) (+1)‎ . . (Bot: moving all {{mpu}} to {{chip}}) (undo)
(cur | prev) 17:02, 30 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,740 bytes) (0)‎ . . (Bot: corrected param) (undo)
(cur | prev) 21:44, 22 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,740 bytes) (-219)‎ . . (Bot: change package to new layout) (undo)
(cur | prev) 00:41, 11 December 2016‎ ChipIt (talk | contribs)‎ . . (3,959 bytes) (-1)‎ . . (undo)
(cur | prev) 22:35, 10 December 2016‎ ChipIt (talk | contribs)‎ . . (3,960 bytes) (+188)‎ . . (undo)
(cur | prev) 22:23, 10 December 2016‎ ChipIt (talk | contribs)‎ . . (3,772 bytes) (+959)‎ . . (undo)
(cur | prev) 19:50, 10 December 2016‎ ChipIt (talk | contribs)‎ . . (2,813 bytes) (+454)‎ . . (undo)
(cur | prev) 18:16, 10 December 2016‎ ChipIt (talk | contribs)‎ . . (2,359 bytes) (+2,359)‎ . . (Created page with "{{cavium title|CN3860-500 EXP}} {{mpu | name = Cavium CN3860-500 EXP | no image = | image = octeon cn38xx.png | image size =...")

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN3860-500 EXP - Cavium#package +
base frequency	500 MHz (0.5 GHz, 500,000 kHz) +
core count	16 +
core name	cnMIPS +
designer	Cavium +
family	OCTEON +
first announced	August 22, 2005 +
first launched	August 22, 2005 +
full page name	cavium/octeon/cn3860-500bg1521-exp +
has ecc memory support	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for regular expression	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	640 KiB (655,360 B, 0.625 MiB) +
l1d$ description	64-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	64-way set associative +
l1i$ size	512 KiB (524,288 B, 0.5 MiB) +
l2$ description	8-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	August 22, 2005 +
main image	+
manufacturer	TSMC +
market segment	Networking +
max cpu count	1 +
max memory	16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN3860-500 EXP +
name	Cavium CN3860-500 EXP +
package	FCBGA-1521 +
part number	CN3860-500BG1521-EXP +
process	130 nm (0.13 μm, 1.3e-4 mm) +
series	CN3800 +
smp max ways	1 +
supported memory type	DDR2-800 +
technology	CMOS +
thread count	16 +
word size	64 bit (8 octets, 16 nibbles) +

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