Revision history of "cavium/octeon/cn3005-400bg350-cp"

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(cur | prev) 15:10, 13 December 2017‎ ChippyBot (talk | contribs)‎ m . . (3,891 bytes) (+1)‎ . . (Bot: moving all {{mpu}} to {{chip}}) (undo)
(cur | prev) 16:49, 30 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,890 bytes) (0)‎ . . (Bot: corrected param) (undo)
(cur | prev) 21:20, 23 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,890 bytes) (-27)‎ . . (Bot: Automated text replacement (-\| electrical += Yes +)) (undo)
(cur | prev) 15:49, 10 December 2016‎ ChipIt (talk | contribs)‎ . . (3,917 bytes) (-29)‎ . . (→‎Features) (undo)
(cur | prev) 14:57, 9 December 2016‎ ChipIt (talk | contribs)‎ . . (3,946 bytes) (+7)‎ . . (undo)
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(cur | prev) 05:24, 8 December 2016‎ ChipIt (talk | contribs)‎ . . (2,777 bytes) (+9)‎ . . (undo)
(cur | prev) 05:16, 8 December 2016‎ ChipIt (talk | contribs)‎ . . (2,768 bytes) (+2,768)‎ . . (Created page with "{{cavium title|CN3005 400 MHz CP}} {{mpu | name = Cavium CN3005-400 CP | no image = cn3005-15.png | image = | image size = |...")

base frequency	400 MHz (0.4 GHz, 400,000 kHz) +
core count	1 +
core name	cnMIPS +
designer	Cavium +
family	OCTEON +
first announced	January 30, 2006 +
first launched	May 1, 2006 +
full page name	cavium/octeon/cn3005-400bg350-cp +
has ecc memory support	false +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	24 KiB (24,576 B, 0.0234 MiB) +
l1d$ description	64-way set associative +
l1d$ size	8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description	2-way set associative +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
l2$ description	2-way set associative +
l2$ size	0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
ldate	May 1, 2006 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory	2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth	0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN3005-400 CP +
name	Cavium CN3005-400 CP +
part number	CN3005-400BG350-CP +
power dissipation	3 W (3,000 mW, 0.00402 hp, 0.003 kW) +
process	130 nm (0.13 μm, 1.3e-4 mm) +
series	CN3000 +
smp max ways	1 +
supported memory type	DDR2-533 +
technology	CMOS +
thread count	1 +
word size	64 bit (8 octets, 16 nibbles) +

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